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vpx 3220 a, vpx 3216 b, vpx 3214 c video pixel decoders edition july 1, 1996 6251-368-2pd preliminary data sheet micronas intermetall micronas
vpx 3220 a, vpx 3216 b, vpx 3214 c preliminary data sheet micronas intermetall 2 contents page section title 5 1. introduction 5 1.1. difference between vpx 3220 a and vpx 3216 b 5 1.2. difference between vpx 3216 b and vpx 3214 c 5 1.3. system architecture 6 2. functional description 6 2.1. analog front-end 6 2.1.1. input selector 6 2.1.2. clamping 6 2.1.3. automatic gain control 7 2.1.4. digitally controlled clock oscillator 7 2.1.5. analog-to-digital converters 7 2.2. color decoder 7 2.2.1. if-compensation 7 2.2.2. demodulator 8 2.2.3. chrominance filter 8 2.2.4. frequency demodulator 8 2.2.5. burst detection 9 2.2.6. color killer operation 9 2.2.7. delay line/comb filter 10 2.2.8. luminance notch filter 11 2.2.9. ycbcr color space 11 2.3. component processing 12 2.3.1. horizontal resizer 13 2.3.2. skew correction 13 2.3.3. contrast, brightness, and noise shaping 13 2.3.4. c b c r upsampler 14 2.4. color space stage 14 2.4.1. color space selection 15 2.4.2. compression 24 8 bits 15 2.4.3. inverse gamma correction 15 2.4.4. alpha key 15 2.4.4.1. alpha key as static control signal 16 2.5. output pixel format 16 2.5.1. output ports 16 2.5.2. output port formats
preliminary data sheet vpx 3220 a, vpx 3216 b, vpx 3214 c micronas intermetall 3 contents, continued page section title 18 3. video timing 18 3.1. video reference signals href and vref 18 3.1.1. href 18 3.1.2. vref 18 3.1.3. odd/even 18 3.2. operational modes 18 3.2.1. open mode 18 3.2.2. forced mode 20 3.2.3. scan mode 20 3.2.4. transition behavior 23 3.3. windowing the video field 24 3.4. video data transfer 24 3.4.1. synchronous output 26 3.4.2. asynchronous output 27 4. serial interface a 27 4.1. overview 27 4.2. i 2 c-bus interface 27 4.3. reset and ic address selection 27 4.4. protocol description 28 4.5. fp control and status registers 29 4.6. i 2 c initialization 29 4.7. i 2 c control and status registers 35 4.8. fp control and status registers 41 4.9. initial values on reset 43 5. jtag boundary-scan, test access port (tap) 43 5.1. general description 43 5.2. tap architecture 43 5.2.1. tap controller 43 5.2.2. instruction register 43 5.2.3. boundary scan register 44 5.2.4. bypass register 44 5.2.5. device identification register 44 5.2.6. master mode data register 44 5.3. exception to ieee 1149.1 44 5.4. ieee 1149.11990 spec adherence 44 5.4.1. instruction register 44 5.4.2. public instructions 44 5.4.3. self-test operation 45 5.4.4. test data registers 45 5.4.5. boundary-scan register 45 5.4.6. device identification register 45 5.4.7. performance
vpx 3220 a, vpx 3216 b, vpx 3214 c preliminary data sheet micronas intermetall 4 contents, continued page section title 49 6. specifications 49 6.1. outline dimensions 50 6.2. pin connections and short descriptions 53 6.3. pin descriptions 54 6.4. pin configuration 55 6.5. pin circuits 57 6.6. electrical characteristics 57 6.6.1. absolute maximum ratings 59 6.6.2. recommended operating conditions 59 6.6.3. power consumption 60 6.6.4. characteristics, reset 60 6.6.5. input characteristics of res and oe 60 6.6.6. recommended crystal characteristics 60 6.6.7. xtal input characteristics 61 6.6.8. characteristics, analog video inputs 62 6.6.9. characteristics, analog front-end and adcs 63 6.6.10. characteristics of the jtag interface 64 6.6.10.1. timing of the test access port tap 65 6.6.11. characteristics, i 2 c-bus interface 66 6.6.12. digital video interface 68 6.6.12.1. characteristics, synchronous mode, 13.5 mhz data rate, asingle clocko 69 6.6.12.2. characteristics, synchronous mode, 20.25 mhz data rate, asingle clocko 70 6.6.12.3. characteristics, synchronous mode, 13.5 mhz data rate, adouble clocko 71 6.6.12.4. characteristics, asynchronous mode 73 6.6.13. characteristics, ttl output driver 74 6.6.13.1. ttl output driver type a 74 6.6.13.2. ttl output driver type b 75 6.6.14. characteristics, enable/disable of output signals 77 1. introduction for addendum 77 2. new output timing newvact 79 3. low power mode 80 4. data sheet history
vpx 3220 a, vpx 3216 b, vpx 3214 c preliminary data sheet micronas intermetall 5 video pixel decoder family release notes: revision bars indicate significant changes to the previous edition. 1. introduction the video pixel decoder (vpx) is a full-feature video ac- quisition ic for consumer video and multimedia applica- tions. all of the processing necessary to convert an ana- log video signal into a digital component stream has been integrated onto a single 44-pin ic. its notable fea- tures include: single chip multistandard color decoding ntsc/pal/ secam/s-vhs, ntsc with chroma comb filter. two 8-bit video a/d converters with clamping and au- tomatic gain control (agc) four analog inputs with integrated selector for 3 composite video sources (cvbs), or 2 yc sources (svhs), or 2 composite video sources and one yc source. automatic standard detection horizontal and vertical sync detection for all standards hue, brightness, contrast, and saturation control horizontal resizing between 32 and 1056 pixel/line vertical resizing by line dropping high quality anti-aliasing filter (vpx 3220 a only) itu-r601 level compatible yc b c r (4:4:4, 4:2:2, or 4:1:1) or g -corrected rgb 4:4:4 (15, 16, or 24 bits) compressed video (dpcm 8 bit) (vpx 3214 c supports only ycrcb 4:2:2) alpha key generation (only vpx 3220 a, and vpx 3216 b) 8-bit or 16-bit synchronous output mode asynchronous output mode via fifo with status flags vbi bypass mode for teletext, closed caption, and intercast 44-pin plastic package (plcc, tqfp) total power consumption under 1 w i 2 c serial control, selectable power-up default state on-chip clock generation ieee 1149.1 (jtag) boundary scan interface vpx 3220 a, vpx 3216 b, and vpx 3214 c are pin and software compatible, but differ slightly in the feature set. 1.1. difference between vpx 3220 a and vpx 3216 b vpx 3220 a performs low-pass filtering before resam- pling the data, whereas vpx 3216 b does not. for more info, see fig. 11 and refer to section 2.3. 1.2. difference between vpx 3216 b and vpx 3214 c the vpx 3214 c is based on the vpx 3216 b but without color space conversion. vpx 3214 c supports only yc b c r 4:2:2. 1.3. system architecture the block diagram in fig. 11 illustrates the signal flow through the vpx. a sampling stage performs 8-bit a/d conversion, clamping, and agc. the color decoder sep- arates the luma and chroma signals, demodulates the chroma, and filters the luminance. a sync slicer detects the sync edge and computes the skew relative to the sample clock. the component processing stage resizes the ycbcr samples, adjusts the contrast and bright- ness, and interpolates the chroma. the color space stage contains a dematrix, a g 1 correction, a dpcm-like encoder, and an alpha key generator. the format stage arranges the samples into the selected byte format and (in the case of asynchronous output) buffers the data for output. fig. 11: block diagram of the vpx mux mux sync 2 x a/d color decoder luma filter chroma demod. sampling line store horizontal resizer contrast & brightness chroma upsample component processing color space y c b c r skew chroma & luma filter vpx 3220 a only ycbcr yuv > rgb inverse gamma dpcm, & alpha key ycbcr/ rgb alpha key format & fifo & mux output mux port h/v sync a b clock mux port cvbs/y chroma
vpx 3220 a, vpx 3216 b, vpx 3214 c preliminary data sheet micronas intermetall 6 2. functional description 2.1. analog front-end this block provides the analog interfaces to all video in- puts and mainly carries out analog-to digital conversion for the following digital video processing. a block dia- gram is given in fig. 22. most of the functional blocks in the front-end are digitally controlled (clamping, agc, and clock-dco). the con- trol loops are closed by the fast processor (`fp') em- bedded in the decoder. 2.1.1. input selector up to four analog inputs can be connected. they all must be ac-coupled. two of them (vin2 and vin3) are for in- put of composite video or s-vhs luma signal. these in- puts are clamped to the sync back porch and are ampli- fied by a variable gain amplifier. one input (cin) is for connection of s-vhs carrier-chrominance signal. this input is internally biased and has a fixed gain amplifier. the fourth one (vin1) can be used for both functions (see fig. 22). for possible combinations and types of input signals, see fig. 21. cvbs s-vhs 3 2 02 1 0 cvbs luma chroma vin1 vin2 vin3 cin fig. 21: combinations and types of input signals 2.1.2. clamping the composite video input signals are ac-coupled to the ic. the clamping voltage is stored on the coupling ca- pacitors and is generated by digitally controlled current sources. the clamping level is the back porch of the vid- eo signal. s-vhs chroma is also ac-coupled. the input pin is internally biased to the center of the adc input range. 2.1.3. automatic gain control a digitally working automatic gain control adjusts the magnitude of the selected baseband by +6/4.5 db in 64 logarithmic steps to the optimal range of the adc. output mux input mux clamp level bias/ dac freq. frequ. doubler frequ. divider 20.25 mhz dac gain adc agc reference generation adc 8 8 vin3 level clamp +6/4.5 db select fig. 22: analog front-end vin2 vin1 cin to color decoder digital chroma digital cvbs or y system clocks dvco 150 ppm cvbs/y cvbs/y cvbs/ y/c c
vpx 3220 a, vpx 3216 b, vpx 3214 c preliminary data sheet micronas intermetall 7 2.1.4. digitally controlled clock oscillator the clock generation is also a part of the analog front- end. the crystal oscillator is controlled digitally by the control processor; the clock frequency can be adjusted within 150 ppm if the recommended crystal is used. 2.1.5. analog-to-digital converters two adcs are provided to digitize the input signals. each converter runs with 20.25 mhz and has 8-bit reso- lution. an integrated bandgap circuit generates the re- quired reference voltages for the converters. the two adcs are of a 2-stage subranging type. 2.2. color decoder in this block, the entire luma/chroma separation and multistandard color demodulation is carried out. the col- or demodulation uses an asynchronous clock, thus al- lowing a unified architecture for all color standards. both luma and chroma are processed to an orthogonal sampling raster. luma and chroma delays are matched. the total delay of the decoder is adjustable by a fifo memory. therefore, even when the display processing delay is included, a processing delay of exactly 64 m sec can be achieved. the color decoder output is yc r c b in a 4:2:2 format. 2.2.1. if-compensation with off-air or mistuned reception, any attenuation at higher frequencies or asymmetry around the color sub- carrier is compensated. three different settings of the if-compensation are possible: flat (no compensation) 6 db/octave 12 db/octave fig. 23: frequency response of chroma if-com- pensation 2.2.2. demodulator the entire signal (which might still contain luma) is now quadrature-mixed to the baseband. the mixing frequen- cy is equal to the subcarrier for pal and ntsc, thus achieving the chroma demodulation. for secam, the mixing frequency is 4.286 mhz giving the quadrature baseband components of the fm modulated chroma. after the mixer, a lowpass filter selects the chroma com- ponents; a downsampling stage converts the color dif- ference signals to a multiplexed half-rate data stream. the subcarrier frequency in the demodulator is gener- ated by direct digital synthesis; therefore, substandards such as pal 3.58 or ntsc 4.43 can also be demodu- lated.
vpx 3220 a, vpx 3216 b, vpx 3214 c preliminary data sheet micronas intermetall 8 2.2.3. chrominance filter the demodulation is followed by a lowpass filter for the color difference signals for pal/ntsc. secam requires a modified lowpass function with a bell-filter characteris- tic. at the output of the lowpass filter, all luma information is eliminated. the lowpass filters are calculated in time multiplex for the two color signals. three bandwidth settings (narrow, normal, broad) are available for each standard. the filter passband can be shaped with an extra peaking term at 1.25 mhz. db mhz 0 01 2 34 5 10 20 30 40 50 db mhz 0 01 2 34 5 10 20 30 40 50 pal/ ntsc secam narrow broad normal fig. 24: frequency response of chroma filters 2.2.4. frequency demodulator the frequency demodulator for demodulating the secam signal is implemented as a cordic-structure. it calculates the phase and magnitude of the quadrature components by coordinate rotation. the phase output of the cordic processor is differen- tiated to obtain the demodulated frequency. after a pro- grammable deemphasis filter, the dr and db signals are scaled to standard c r c b amplitudes and fed to the cross- over-switch. db mhz 0 0.01 0.1 1.0 1 2 3 4 5 6 7 8 9 10 11 fig. 25: frequency response of secam deemphasis 2.2.5. burst detection in the pal/ntsc-system, the burst is the reference for- the color signal. the phase and magnitude outputs of the cordic are gated with the color key and used for controlling the phase-lock-loop (apc) of the demodula- tor and the automatic color control (acc) in pal/ntsc. the acc has a control range of +30...6 db. for secam decoding, the frequency of the burst is mea- sured. thus, the current chroma carrier frequency can be identified and is used to control the secam proces- sing. the burst measurements also control the color kill- er operation.
vpx 3220 a, vpx 3216 b, vpx 3214 c preliminary data sheet micronas intermetall 9 2.2.6. color killer operation the color killer uses the burst-phase, -frequency mea- surement to identify a pal/ntsc or secam color sig- nal. for pal/ntsc, the color is switched off (killed) as long as the color subcarrier pll is not locked. for secam, the killer is controlled by the toggle of the burst frequency. the burst amplitude measurement is used to switch-off the color if the burst amplitude is below a pro- grammable threshold. thus, color will be killed for very noisy signals. the color amplitude killer has a program- mable hysteresis. 2.2.7. delay line/comb filter the color decoder uses one fully integrated delay line. only active video is stored. the delay line application depends on the color stan- dard: ntsc: combfilter or color compensation pal: color compensation secam: crossover-switch in the ntsc compensated mode, fig. 26 c), the color signal is averaged for two adjacent lines. therefore, cross-color distortion and chroma noise is reduced. in the ntsc combfilter mode, fig. 26 d), the delay line is in the composite signal path, thus allowing reduction of cross-color components, as well as cross-luminance. the loss of vertical resolution in the luminance channel is compensated by adding the vertical detail signal with removed color information. chroma notch filter chroma process. cvbs y 1 h delay cvbs chroma process. notch filter y chroma process. luma y a) conventional b) s-vhs d) comb filter fig. 26: ntsc color decoding options c c r b c c r b c c r b notch filter 1 h delay chroma process. cvbs y c) compensated c c r b chroma notch filter 1 h delay 8 chroma process. cvbs y mux chroma process. luma y notch filter 1 h delay chroma process. cvbs y 1 h delay a) conventional b) s-vhs fig. 27: pal color decoding options fig. 28: secam color decoding c c r b c c r b c c r b
vpx 3220 a, vpx 3216 b, vpx 3214 c preliminary data sheet micronas intermetall 10 2.2.8. luminance notch filter if a composite video signal is applied, the color informa- tion is suppressed by a programmable notch filter. the position of the filter center frequency depends on the subcarrier frequency for pal/ntsc. for secam, the notch is directly controlled by the chroma carrier fre- quency. this considerably reduces the cross-lumi- nance. the frequency responses and the delay charac- teristics of all three systems are shown below. pal notch filter nsec mhz 100 02 4 68 10 90 80 70 60 50 40 30 20 10 0 db mhz 10 02 4 68 10 0 10 20 30 40 secam notch filter nsec mhz 100 02 4 68 10 90 80 70 60 50 40 30 20 10 0 db mhz 10 02 4 68 10 0 10 20 30 40 nsec mhz 100 02 4 68 10 90 80 70 60 50 40 30 20 10 0 ntsc notch filter db mhz 10 02 4 68 10 0 10 20 30 40 fig. 29: frequency responses and time delay characteristics for pal, secam, and ntsc
vpx 3220 a, vpx 3216 b, vpx 3214 c preliminary data sheet micronas intermetall 11 2.2.9. ycbcr color space the color decoder outputs luminance and two chromi- nance signals at a sample clock of 20.25 mhz. active video samples are flagged by a separate reference sig- nal. the number of active samples is 1056 for all stan- dards (525 lines and 625 lines). the representation of the chroma signals is the itur-601 digital studio stan- dard. in the following equations, the rgb signals are already gamma-weighted. y = 0.299*r + 0.587*g + 0.114*b (ry) = 0.701*r 0.587*g 0.114*b (by) = 0.299*r 0.587*g + 0.886*b in the color decoder, the weighting for both color differ- ence signals is adjusted individually. the default format will have the following specification: y = 224*y + 16 (pure binary), c r = 224*(0.713*(ry)) + 128 (offset binary), c b = 224*(0.564*(by)) + 128 (offset binary). 2.3. component processing recovery of the ycbcr components by the decoder is followed by horizontal resizing and skew compensation. contrast enhancement with noise shaping can also be applied to the luminance signal. the cbcr samples are interpolated to create a 4:4:4 format. fig. 210 illustrates the signal flow through the compo- nent processing stage. the ycbcr 4:2:2 samples are separated into a luminance path and a chrominance path. the luma filtering and chroma filtering blocks apply fir lowpass filters with selectable cutoff frequen- cies. these filters are available only in vpx 3220 a. the resize and skew blocks alter the effective sampling rate and compensate for horizontal line skew. the ycbcr samples are buffered in a fifo for continuous read out at a fixed clock rate. in the luminance path, the contrast and brightness can be varied and noise shaping applied. in the chrominance path, interpolation is used to generate a 24-bit/pixel output stream (4:4:4 format). resize skew resize skew sequence control f i f o 16 bit contrast & brightness c b c r upsampler active video reference latch luma filter chroma filter y out cb out cr out y in cbcr in luma phase shift chroma phase shift fig. 210: component processing stage vpx 3220 a only
preliminary data sheet vpx 3220 a, vpx 3216 b, vpx 3214 c micronas intermetall 12 2.3.1. horizontal resizer the horizontal resizer alters the sampling raster of the video signal, thereby varying the number of pixels in the active portion of the video line. the number of pixels per line is selectable within the range from 1056 to 32 in in- crements of 2 pixels. in the digital domain, this is done by lowpass filtering (vpx 3220 a only), followed by a programmable phase shift with an allpass filter. the vpx 3220 a is equipped with a battery of 32 fir fil- ters to cover the four octave operating range of the resiz- er. fig. 213 shows the magnitude response of the en- tire filter set. all filters exhibit a minimum stop band attenuation of at least 35 db. figures 211 and 212 illustrate the performance of the filters in detail. filter selection is performed by an internal processor based on the selected resizing factor. this automated selection is optimized for best visual performance but can be fine tuned to satisfy different needs. it is also pos- sible to override the internal selection completely. in that case, filters are selected over i 2 c bus. the resize and skew block performs programmable phase shifting with subpixel accuracy. in the luminance path, a linear interpolation filter provides a phase shift between 0 and 31/32 in steps of 1/32. this corresponds to an accuracy of 1.6 ns. the chrominance signal can be shifted between 0 and 3/4 in steps of 1/4. figs. 214 through 217 show the the transfer function of the two skew filters. fig. 211: resizer filters for the upper octave fig. 212: resizer filters for the lower three octaves fig. 213: magnitude response of resizer filter bank (vpx 3220 a only)
vpx 3220 a, vpx 3216 b, vpx 3214 c preliminary data sheet micronas intermetall 13 db mhz 0 02 4 68 10 1 2 3 4 5 6 7 8 2 1 clocks mhz 2.5 02 4 68 10 2.3 2.1 1.9 1.7 1.5 1.3 1.1 0.9 0.7 0.5 0.6 0.7 0.8 0.9 1.0 0.1, 0.9 0.2, 0.8 0.3, 0.7 0.4, 0.6 0.5 parameter: a, 32 steps 0.4 0.3 0.2 0.1 0 0.5 0, 1.0 parameter: a, 32 steps fig. 214: luminance skew filter magnitude frequency response fig. 215: luminance skew filter group delay characteristics db 0 1 2 3 4 5 6 7 8 2 1 mhz 01 2 34 5 mhz 01 2 34 5 clocks 5.0 4.6 4.2 3.8 3.4 3.0 2.6 2.2 1.8 1.4 1 4.0 2.0 0.5 0.8 1.0 0.2 0 0.5 0.25 0, 1.0 parameter: a, 4 steps parameter: a, 4 steps fig. 216: chrominance skew filter magnitude frequency response fig. 217: chrominance skew filter group delay characteristics 2.3.2. skew correction the vpx delivers orthogonal pixels with a fixed clock even in the case of non-broadcast signals with substan- tial horizontal jitter (vcrs, laser disks, certain portions of the 6 o'clock news...). this is achieved by highly accurate sync slicing com- bined with post correction. immediately after the analog input is sampled, a horizontal sync slicer tracks the posi- tion of sync. this slicer evaluates, to within 1.6 ns., the skew between the sync edge and the edge of the pixel- clock. this value is passed as a skew on to the phase shift filter in the resizer. the skew is then treated as a fixed initial offset during the resizing operation. 2.3.3. contrast, brightness, and noise shaping i out = c * i in + b c = 0...63/32 in 64 steps b = 127...128 in 256 steps a selectable gain and offset can be applied to the lumi- nance samples. both the gain and offset factors can be set externally via i 2 c serial control. fig. 218 gives a functional description of this circuit. first, a gain is ap- plied, yielding a 10-bit luminance value. the conversion back to 8-bit is done using one of three selectable tech- niques: simple rounding, 1-bit error diffusion, or 2-bit er- ror diffusion. contrast select rounding 1 bit err. diff. 2 bit err. diff. brightness i 2 c registers fig. 218: contrast and brightness adjustment 2.3.4. c b c r upsampler simple interpolation is used to convert the 4:2:2 video samples up to the 4:4:4 format. the cbcr samples are upsampled and then band limited with the linear phase fir kernel. the passband of this filter covers the entire chroma spectrum present in analog composite and s-vhs signals.
preliminary data sheet vpx 3220 a, vpx 3216 b, vpx 3214 c micronas intermetall 14 2.4. color space stage the color space stage (fig. 219) of the vpx 3220 a and vpx 3216 b optionally performs a series of conversions in the color space and component format. generation of an alpha key signal, compression using quantized differ- ential coding, and inverse gamma correction are pro- grammable options. beginning with the 24-bit/pixel ycbcr input signal, two other component formats (4:2:2 and 4:1:1) can be gen- erated by simple downsampling of the chroma. alterna- tively, the 24-bit ycbcr can be dematrixed to produce 24-bit rgb. the rgb components can either be output directly or further quantized to yield other quantization formats such as 16-bit (r:5 g:6 b:5) or 15-bit (r:5 g:5 b:5) the table below summarizes the supported output signal formats. compo- nents sampling format quantization format bits/ pixel ycbcr 4:4:4 4:2:2 4:1:1 4:4:4 (compressed) 8 8 8 8 8 8 8 8 8 8 8 8 24 16 12 8 rgb 4:4:4 4:4:4 4:4:4 8 8 8 5 6 5 5 5 5 24 16 15 2.4.1. color space selection 1 0 1.403 1 0.344 0.714 1 1.773 0 y cb cr r g b an optional dematrix stage converts the ycbcr 4:4:4 data into rgb using the matrix equations specified in the itur 601 recommendation (shown above). the satura- tion control in the color decoder is first selected to pro- duce c b and c r , the itur studio chrominance norm. in the dematrix computation, the full 8-bit resolution is maintained. alpha key dematrix compression 4:4:4 4:1:1 4:4:4 4:2:2 888 565 888 555 quantization downsampling ycbcr ycbcr ycbcr 12 bit / pixel 16 bit / pixel 24 bit / pixel ycbcr 8 bit / pixel rgb 24 bit / pixel rgb 16 bit / pixel rgb 15 bit / pixel s e l e c t fi g . 219: the color space sta g e g -1
vpx 3220 a, vpx 3216 b, vpx 3214 c preliminary data sheet micronas intermetall 15 2.4.2. compression 24 8 bits a variant of the time-honored dpcm coding technique is available to compress the 24-bit ycbcr 4:4:4 signal to an 8-bit per pixel signal. the technique combines differ- ential coding, companding, and adaptive subsampling of the chrominance. for the most natural image materi- al, the resulting bandwidth savings are purchased at a modest loss of amplitude resolution, which appears mostly as high frequency noise. signals encoded in this form are readable by decoders, which are embedded in commercially available ics (ramdacs, back-end ana- log encoders, etc...). different techniques are used to code the luminance and the two chroma signals. for the luma, the difference be- tween 8-bit luma value and a computed reference is companded to a 5-bit value for transmission. the com- puted reference is simply the 8-bit value of the nearest horizontal neighbor as it appears at the decoder. each decoded luminance sample is therefore used as a pre- diction for the next pixel. this, in turn, requires that the encoder contains almost a complete decoder as a sub- set. the chrominance samples are encoded in a similar fashion. the samples of each chrominance component are ordered into non-overlapping groups of four. for each group, one of the four samples is selected as a rep- resentative value. for each representative pixel, the rel- ative position and companded differential amplitude are computed for transmission. the position data is relative to the beginning of the group and is encoded as a 2-bit word. the difference between the 8-bit value of the sam- ple and the decoded reference value of the previous group is companded to a 5-bit word. 2.4.3. inverse gamma correction today, most broadcast video sources anticipate the dis- play on conventional crts by predistorting the rgb sig- nals with a gamma function (shown below) i' = ci g + i 0 g 2.2 c, i 0 = constants i {r, g, b}... linear intensity however, for video processing in a computer, linear space (no gamma distortion) is often the representation of choice. the vpx provides two options for gamma re- moval. both conform to the basic formula: i = i' (1 /g) these two g 1 functions are realized as fixed entries in rom. the first table compensates for a g = 1.4. the se- cond table compensates for a g = 2.2. 2.4.4. alpha key a 1-bit threshold select signal can be generated for ev- ery pixel in the ycbcr 4:4:4 signal. using six registers, an upper and a lower threshold is separately defined for each of the y, c b , and c r components. these six register values define a cube in yc b c r space. equality is always included in comparison. for each pixel, an alpha bit is generated, which signals whether the pixel lies inside or outside this cube. a 3-point horizontal median filter is available to mitigate the effects of impulse noise.the al- pha signal is fed out through the alpha pin, which is in turn multiplexed with jtag tdo function (see chapter 5, sections 5.1. and 5.3.). when there is no jtag activ- ity, the tdo pin is used for the alpha signal. polarity of this signal (high active or low active) can be pro- grammed using i 2 c. 2.4.4.1. alpha key as static control signal the alpha pin can also be used as a static control signal. when doing so, all comparators have to be set to their respective maximal or minimal values. ymin = 00 ymax = ff umin = 80 umax = 7f vmin = 80 vmax = 7f in this case, the alpha signal will always be correct and the output state (high or low) can be selected through the polarity bit (keyinv bit in format register).
preliminary data sheet vpx 3220 a, vpx 3216 b, vpx 3214 c micronas intermetall 16 2.5. output pixel format the output formatting stage (fig. 220) receives the vid- eo samples from the color component stage, performs the necessary bit packing, buffers the data for transmis- sion, and channels the output via one or both 8-bit ports. data transfer can be either synchronous to an internally generated pixel clock or asynchronous with fifo and status signals. format section controls: byte formats (bit order) number of ports (a only or both a and b) clock speed (single or double). the video samples (and alpha key) arrive from the color component stage at one of two pixel transport rates: 13.5 mhz or 20.25 mhz. this clock rate is selectable via i 2 c command. however, the use of the 13.5 mhz clock assumes that the resizer is reducing the number of ac- tive samples per line to a maximum of 768 pixels. 2.5.1. output ports the two 8-bit ports produce ttl level signals coded in binary offset. the ports can be tristated either via the output enable pin (oe ) or via i 2 c commands. 2.5.2. output port formats the format of output data depends on three parameters: the selected signal format, the number of active ports, and the output clock rate. for a given clock rate and number of active ports, a subset of these output formats is supported. figures 221 and 222 illustrate this de- pendency. all single port transfers use port a only. bus shuffle output fifo output multiplex alpha key port 1 port 2 oe clock generation pixclk fe hf syncr / asyncr 1 24 24 24 1 1 8 8 video samples alpha key 8 8 i 2 c reg fig. 220: output formatting stage
vpx 3220 a, vpx 3216 b, vpx 3214 c preliminary data sheet micronas intermetall 17 single clock (port a only) t 1 f 1 f 2 t 2 f 1 f 2 f 1 f 2 f 1 f 2 t 1 ycbcr 4:1:1 compressed 70 0, u a 1, u a 0 u a 4, u a 3, u a 2 0, v a 1 v a 0 v a 4, v a 3, v a 2 y a 4 ..... y a 0 y b 4 ..... y b 0 y c 4 ..... y c 0 y d 4 ..... y d 0 ycbcr 4:2:2 (mode 1) ycbcr 4:2:2 (mode 2) rgb 5 5 5 + a rgb 5 6 5 y a 7 ...... y a 0 u a 7 ...... u a 0 y b 7 ...... y b 0 v a 7 ...... v a 0 a r 7 ..... r 3 g 7 , g 6 g 5 ... g 3 b 7 .... b 3 r 7 ..... r 3 g 7 ... g 5 g 4 ... g 2 b 7 .... b 3 t 2 t 3 t 4 t 1 f 1 f 2 t 2 f 1 f 2 y a 7 ...... y a 0 y b 7 ...... y b 0 u a 7 ...... u a 0 v a 7 ...... v a 0 fig. 221: byte formats for single port transfers note: all single port transfers use port a only note: u, v c b , c r double clock (port a only) single clock port a port b ycbcr 4:2:2 v a 7 ...... v a 0 rgb 5 5 5 + a rgb 5 6 5 b 7 .... b 3 g 4 ... g 2 r 7 ....r 3 g 7 ... g 5 ycbcr 4:1:1 b 7 .... b 3 g 5 ... g 3 r 7 ....r 3 g 7 , g 6 a y b 7 ...... y b 0 y a 7 ...... y a 0u a 7 ...... u a 0 t 1 t 2 y b 7 ...... y b 0 y a 7 ...... y a 0 u a 7 u a 6 v a 7 v a 6 t 1 t 2 y d 7 ...... y d 0 y c 7 ...... y c 0 t 3 t 4 0...0 u a 5 u a 4 v a 5 v a 4 0...0 u a 3 u a 2 v a 3 v a 2 0...0 u a 1 u a 0 v a 1 v a 0 0...0 v a 7 ...... v a 0 y a 7 ...... y a 0u a 7 ...... u a 0 f 1 f 2 f 1 f 2 double clock u a 7 ...... u a 0 r 7 ..... r 0 b 7 ..... b 0 g 7 ..... g 0 g 7 ..... g 0 ycbcr 4:4:4 rgb 8 8 8 fig. 222: byte formats for double port transfers
preliminary data sheet vpx 3220 a, vpx 3216 b, vpx 3214 c micronas intermetall 18 3. video timing 3.1. video reference signals href and vref the vpx generates two video reference signals; a hori- zontal reference (href) and a vertical reference (vref). these two signals are generated by program- mable hardware and can be either free running or syn- chronous to the analog input video. the video line stan- dard (625/50 or 525/60) can be either inferred from the analog input video or forced via i 2 c command from the external controller. the polarity of the two signals is indi- vidually selectable. the circuitry which produces the vref and href sig- nals has been designed to provide a stable, robust set of timing signals, even in the presence of erratic behav- ior at the analog video input. depending on the selected operating mode, the period of the href and vref sig- nals are guaranteed to remain within a fixed range. these video reference signals can therefore be used to synchronize the external components of a video subsys- tem (for example the neighboring ics of a pc add-in card). 3.1.1. href fig. 31 illustrates the timing of the href signal relative to the analog input. the active period of href is fixed and is always equal to the length of the active portion of a video signal. therefore, regardless of the video line standard, href is active for 1056 periods of the 20.25 mhz system clock. the total period of the href signal is expressed as f nominal and depends on the video line standard. f nominal analog video input href vpx delay fig. 31: href relative to input video 52 m s 3.1.2. vref figs. 32 and 33 illustrate the timing of the vref signal relative to field boundaries of the two tv standards. the length of the vref pulse is programmable in the range between 2 and 9 video lines. 3.1.3. odd/even information on whether the current field is odd or even, is supplied through the relationship between the edge (either leading or trailing) of vref and level of href. this relationship is fixed and shown in figs. 32 and 33. the same information can be supplied to the field/pref pin. the polarity of the signal is program- mable. 3.2. operational modes the relationship between the video timing signals (href and vref) and the analog input video is deter- mined by the selected operational mode. three such modes are available: the open mode , the forced mode , and the scan mode . these modes are selected via i 2 c commands from the external controller. 3.2.1. open mode in the open mode, both the href and the vref signal track the analog video input. in the case of a change in the line standard (i.e. switching between the video input ports), href and vref automatically synchronize to the new input. when no video is present, both href and vref float to the idling frequency of their respective plls. during changes in the video input (drop-out, switching between inputs), the performance of the href and vref signals is not guaranteed. 3.2.2. forced mode in the forced mode , vref and href follow the input video signal within certain tolerances. dedicated hard- ware is used to monitor the frequency of the analog tim- ing. at the moment when the video signal exceeds the allowed timing tolerances, generation of the timing sig- nals is taken over by free running hardware. if the input video is still present, the vpx continually attempts to re- synchronize to it. for each of the two video line standards (625/50 and 525/60), there exist normative values for the period of both the href and vref signals. many analog input signals deviate significantly from these norms (example, consumer vcrs in their shuttle modes). in the forced mode, monitoring hardware is used to impose an upper boundary on the deviation. the maximum allowed hori- zontal deviation is 24 m s. the upper boundary for verti- cal deviation is 11% of the number of lines in the se- lected line standard (625/50: 35 lines, 525/60: 30 lines) during the free-running operation, video output data is suppressed. if the vpx successfully resynchronizes, video output resumes. the specific method used to sup- press the output video depends on the transfer mode (synchronous or asynchronous).
vpx 3220 a, vpx 3216 b, vpx 3214 c preliminary data sheet micronas intermetall 19 1234567 input cvbs (50 hz) href vref 34567 8 910 625 input cvbs (60 hz) 541 t clk20 313 314 315 316 317 318 319 312 320 input cvbs (50 hz) 265 266 267 268 269 270 271 272 273 input cvbs (60 hz) 69 t clk20 href vref fig. 32: vref timing for odd fields fig. 33: vref timing for even fields 541 t clk20 69 t clk20 > 1 t clk20 odd/even 2 .. 9 h > 1 t clk20 odd/even 2 .. 9 h
preliminary data sheet vpx 3220 a, vpx 3216 b, vpx 3214 c micronas intermetall 20 3.2.3. scan mode in the scan mode, the href and vref signals are al- ways generated by free running hardware. they are therefore completely decoupled from the analog input. the output video data is always suppressed. the purpose of the scan mode is to allow the external controller to freely switch between the analog inputs while searching for the presence of a video signal. in- formation regarding the video (standard, source, etc...) can be queried via i 2 c read. in the scan mode, the video line standard of the vref and href signals can be changed via i 2 c command. the transition always occurs at the first frame boundary after the i 2 c command is received. fig. 34, below, demonstrates the behavior of the vref signal during the transition from the 525/60 system to the 625/50 sys- tem (the width of the vertical reference pulse is exagger- ated for illustration). 3.2.4. transition behavior during normal operation, the timing characteristics of the input video can change in response to a number of phenomena: power up/reset, unplugging of the video jack, switching between selected video inputs, etc... the effect of these changes on the video timing signals is de- pendent on the current operational mode. table 31 summarizes this dependency. in the forced mode, it can often occur that the vpx must resynchronize to an analog input signal after a period in free running sync generation. in such a case, it is likely that the internal sync generators are out of phase with the time base of the analog input. maintaining a stable sync signal requires that the transition between time bases occur over several field periods. fig. 35 illustrates the transition between an internal free running vertical sync and a vertical sync of the ana- log input. the top two lines in this figure show the vertical time base of the analog input signal relative to that of the vref generated from the free running clock. both the analog input and free running syncs conform to the same line standard, but the field polarities are out of phase and the offset between field syncs (given by f error ) is greater than the allowed 20 lines. in the forced mode, vertical resynchronization takes place on field boundaries (as opposed to frame bound- aries) and begins immediately after the appearance of the analog input. in the first field after the appearance of this analog video, the period between vref pulse is shortened by 20 lines ( f rec) and the field polarity of the vref is repeated. for each subsequent field, the phase error is reduced by f rec until the two signals are again in phase. because the resynchronization occurs on field bound- aries and because the internally generated sync can be either lengthened or shortened, the maximum value of f error is 313/2 157 lines. with a maximum correction of 20 lines per field, field locking requires a maximum of 8 fields. vref f odd f odd f even f even f odd time 33.367 ms 16.683 ms 40.0 ms 20.0 ms i 2 c command to switch video timing standard selected timing standard becomes active (525/60) (625/50) fig. 34: transition between timing standards
vpx 3220 a, vpx 3216 b, vpx 3214 c preliminary data sheet micronas intermetall 21 f field f odd f even input signal : vertical timing f field f odd f even f odd f error free running vertical sync f odd 1 f even 1 ... f odd f error f rec f field - f rec f rec 2 f rec f odd 2 f even 2 f even 1 f field - f rec 2 f rec f error (3 f rec ) second frame after switch to tracking mode first frame after switch to tracking mode fig. 35: synchronization to analog input
preliminary data sheet vpx 3220 a, vpx 3216 b, vpx 3214 c micronas intermetall 22 table 31: transition behavior as a function of operating mode transition behavior as a function of operating mode transition mode behavior power up / reset forced vref, href: comes up free running (video timing standard read from internal initialization tables) output ports: suppressed open, scan not applicable video no video open vref, href: floats to steady state frequency of internal pll output ports: still enabled but with undefined data. forced vref, href: switches immediately to free running output ports: suppressed until video restored. scan no visible effect on any data or control signals timing signals continue unchanged in free running mode, data ports remain suppressed no video video open vref, href: track the input signal forced no change in timing standard: vref, href: slowly resynchronize. when resynchronization is complete, the timing control switches back from free running to monitored tracking output ports: re-enabled. change in the timing standard: no visible effect on any data or control signals scan vref, href: no change, continues in free running mode output ports: remain suppressed. video video (same timing standard) open vref, href: track the input video immediately output ports: data available immediately after color decoder locks to input. forced vref, href: brief period in free running mode while the timing is resynchronized output ports: suppressed during resynchronization. scan no outwardly visible effect on any data or control signals. timing signals continue unchanged in free running mode, data ports remain disabled. video video (different timing standard) open same as above forced vref, href: switches immediately to free running output ports: suppressed scan same as the case no video video
vpx 3220 a, vpx 3216 b, vpx 3214 c preliminary data sheet micronas intermetall 23 3.3. windowing the video field for each input video field, two non-overlapping windows can be defined. the dimensions of these two windows are supplied via i 2 c commands. the presence of two windows allows separate processing parameters such as filter responses and the number of pixels per line to be selected. external control over the dimensions of the windows is performed by i 2 c writes to a window definition table (windeftab). for each window, a corresponding win- deftab is defined in a table of i 2 c registers. data written to these tables does not become active until the the cor- responding latch bit is set in a control register. a 2-bit flag specifies the field polarity over which the window is ac- tive. vertically, as can be seen in fig. 36, each window is de- fined by a beginning line, a number of lines to be read-in, and a number of lines to be output. each of these values is specified in units of video lines. the option, to separately specify the number of input lines and the number of output lines, enables vertical compression. in the vpx, vertical compression is per- formed via simple line dropping. a nearest neighbor al- gorithm selects the subset of the lines for output. the presence of a valid line is signaled by a reference signal. the specific signal which is used for the blanking de- pends on the transfer mode (synchronous/asynchro- nous). the numbering of the lines in a field of interlace video is dependent on the line standard. figs. 37 and 38 illus- trate the mapping of the window dimensions to the actu- al video lines. the indices on the left are the line num- bers relative to the beginning of the frame. the indices on the right show the numbering used by the vpx. as seen here, the vertical boundaries of windows are de- fined relative to the field boundary. spatially, the lines from field #1 are displayed above identically numbered line 1 window 1 window 2 begin # lines in, # lines out begin # lines in, # lines out fig. 36: vertical dimensions of windows from field #2. for example: on an interlace monitor, line #23 from field #1 is displayed directly above line #23 from field #2. there are a few restrictions to the vertical definition of the windows. windows must not overlap vertically, but can be adjacent. windows must begin af- ter line #6 (i.e. line #7 is the first one allowed) of their re- spective fields. the number of lines out cannot be great- er than the number of lines in (no vertical zooming). the combined height of the two windows cannot exceed the number of lines in the input field. 1 2 5 6 7 8 15 16 17 18 260 259 258 264 265 268 269 270 271 278 279 280 281 521 522 field 1 field 2 261 262 263 1 2 5 6 7 8 15 16 17 18 260 259 258 261 262 263 523 524 525 1 2 5 6 7 8 15 16 17 18 260 259 258 261 262 257 520 257 257 fig. 37: mapping for 525/60 line systems field 1 field 2 314 315 318 319 320 321 335 336 337 338 622 623 624 625 621 1 2 5 6 7 8 22 23 24 25 311 310 309 312 313 308 1 2 5 6 7 8 22 23 24 25 311 310 309 312 313 308 1 2 6 7 8 22 23 24 25 311 310 309 312 308 5 fig. 38: mapping for 625/50 line systems
preliminary data sheet vpx 3220 a, vpx 3216 b, vpx 3214 c micronas intermetall 24 horizontally, the windows are defined by a starting point and a length. the starting point and the length are both given relative to the number of pixels in the active portion of the line (fig. 39). there are some restrictions in the horizontal window definition. the total number of active pixels (npixel) must be an even number. the maximum value for npixel depends on the selected transport clock. for a 20.25 mhz transport clock, the maximum value for npixel is 1056. for a 13.5 mhz transport clock, the maxi- mum value is 800. hlength should also be an even num- ber. obviously, the sum of hbegin and hlength may not be greater than npixel. window boundaries are defined by writing the dimen- sions into the associated windeftab and then setting the corresponding latch bit in the control word. window definition data is latched at the beginning of the next vid- eo frame. once the windeftab data has been latched, the latch bit in the control word is reset. by polling the info-word, the external controller can know when the window boundary data has been read. multiple window definitions within a single frame time are ignored and can lead to error. window h begin 64 m sec 52.15 m sec h length n pixel fig. 39: horizontal dimensions of sampling window 3.4. video data transfer the vpx supports two methods of transfer for the sampled video data: a synchronous mode and an asynchronous mode. both modes support all the byte formats shown in figs. 221 and 222, as well as both alternative transport rates. in both modes, data arrives at the output fifo in an uninterrupted burst with a fixed transport rate. the trans- port rate is selected by the external controller to be either 13.5 mhz or 20.25 mhz. the duration of the burst is measured in clock periods of the transport clock and is equal to the number of pixels per output line. the control signals on the three pins: pixclk, fe /vact, and hf /fsy, llc regulate the data transfer. their func- tion is dependent on the transfer mode (sync., or async.). for the synchronous mode, the signals at these pins are pixclk (internal), vact, and llc (respective- ly). for the asynchronous mode, the signals at these pins are pixclk (external), fe , and hf . 3.4.1. synchronous output in the synchronous transfer mode, data is transferred synchronous to an internally generated pixclk. the frequency of the pixclk is equal to the selected trans- port rate. in the single clock mode, data can be latched onto the falling edge of pixclk. in double clock mode, output data must be latched onto both clock edges. the double clock mode is supported for the 13.5 mhz trans- port rate only. the available transfer bandwidths at the ports are therefore 13.5 mhz, 20.25 mhz (single clock), and 27.0 mhz (double clock). the video data is output in a continuous stream. the pixclk is free running. the vact signal flags the pres- ence of valid output data. fig. 310 illustrates the rela- tionship between the video port data, vact, and pixclk. whenever a line of video data should be sup- pressed (line dropping, switching between analog in- puts), it is done by suppression of the vact signal. fig. 311 illustrates the temporal relationship between the vact and the href signals as a function of the number of pixels per output line and the horizontal di- mensions of the window. the duration of the active peri- od of the href (fig. 311 , points b, d) is fixed. table 32 lists the positions of the vact edges (points a, c) relative to those of href. the llc signal is provided as an additional support for the 13.5 mhz single clock mode. the llc provides a 2x pixclk signal (27 mhz) for interface to external compo- nents which rely on the philips transfer protocols. in the single clock 13.5 mhz mode, the pixel data can be latched onto alternate rising edges of the llc.
vpx 3220 a, vpx 3216 b, vpx 3214 c preliminary data sheet micronas intermetall 25 table 32: relationship of the href to the vact in synchronous transfer mode resizing windowing timing of rising edges timing of falling edges 20.25 mhz transport rate npix/line = 1056 none a = b c = d npix/line < 1056 none a > b c = d npix/line 1056 window begin > 0 a > b window end < 1055 c < d 13.5 mhz transport rate npix/line = 704 a = b c = d 704 < npix/line 768 none a = b c > d npix/line < 704 a > b c = d npix/line 704 window begin > 0 a > b window end < 1055 c < d port data vact pixclk (single clock) d n1 d n d 1 d 2 d n3 d n2 pixclk (double clock) fig. 310: timing for synchronous output 0 1 2 3 0 1 2 3 port data vact pixclk (single edge.) d n1 d n d 1 d 2 d n3 d n2 href ac b d fig. 311: relation between href and vact signals
preliminary data sheet vpx 3220 a, vpx 3216 b, vpx 3214 c micronas intermetall 26 3.4.2. asynchronous output in the asynchronous mode, data is strobed from the vpx by an external clock supplied to the pixclk pin. a 32-pixel fifo buffers the video samples for transfer. two fifo status signals (hf and fe ) arbitrate the trans- fer. the `half full' signal (hf ) indicates that the number of samples present in the fifo has exceeded some pro- grammable threshold (defined over the range of 0 31). the fe signal indicates that the fifo is empty. some implementations of the asynchronous mode re- quire a more detailed understanding of the rates at which the data is written to and read from the 32 pixel output fifo. on the input side of the fifo, sampled vid- eo data from the vpx-core arrives as a continuous burst with a pixel rate equal to that of the transport clock (20 mhz or 13 mhz burst rate). on the output side, the rate at which the fifo is emptied is dependent on the speed of the pixclk and the se- lected clocking mode. in the asynchronous mode, the pixclk is always a single-edge clock. port data 787766521 fifo fullness level pixclk=2*internal transfer rate hf if full-level is 8 fe 32 2110 10 1 2 fig. 312: timing for asynchronous output
vpx 3220 a, vpx 3216 b, vpx 3214 c preliminary data sheet micronas intermetall 27 4. serial interface a 4.1. overview communication between the vpx and the external con- troller is performed serially via the i 2 c-bus (pins scl and sda). there are basically two classes of registers in the vpx. the first class of registers are the directly addressable i 2 c registers. these are registers embedded directly in the hardware. data written to these registers is inter- preted combinatorially directly by the hardware (as in any register driven state machine). these registers are all a maximum of 8 bits wide. the second class of registers are the `fp ram regis- ters': the ram memory of the on-board microcontroller (intermetall's fast processor). data written into this class of registers is read and interpreted by the fp's mi- cro-code. internally, these registers are 12 bits wide. communications with these registers requires i 2 c pack- ets with 16-bit data payloads. communication with both classes of registers (i 2 c and fp ram) is performed via i 2 c. but the format of the i 2 c telegram depends on which type of register is being ad- dressed. 4.2. i 2 c-bus interface the vpx has an i 2 c-bus slave interface and uses i 2 c clock synchronization to slow down the interface if re- quired. the i 2 c-bus interface uses one level of subad- dressing. first, the bus address selects the ic, then a subaddress selects one of the internal registers. the i 2 c interface of the vpx conforms to the i 2 c-bus specification for the fast-mode. it incorporates slope control for the falling edges of the sda and scl signals. if the power supply of the vpx is switched off, both pins scl and sda float. external pull-up devices must be adapted to fulfill the required rise time for the fast-mode. for bus loads up to 200 pf, the pull-up device could be a resistor; for bus loads between 200 pf and 400 pf, the pull-up device can be a current source (3 ma max.) or a switched resistor circuit. 4.3. reset and ic address selection the vpx can respond to one of two possible chip ad- dresses. the address selection is made at reset by an externally supplied level on the pref pin. this level is latched onto the inactive going edge of res . 4.4. protocol description once the reset is complete, the ic is selected by assert- ing a the device address in the address part of a i 2 c transmission. a device address pair is defined as a write address (86 hex or 8e hex) and a read address (87 hex or 8f hex). writing is done by sending the device write ad- dress first, followed by the subaddress byte and one or two data bytes. for reading, the read address has to be transmitted first by sending the device write address (86 hex or 8e hex), followed by the subaddress, a second start condition with the device read address (87 hex or 8f hex) and reading one or two bytes of data. the i 2 c-bus device addresses are a6 a5 a4 a3 a2 a1 a0 r/w hex 1 0 0 0 0 1 1 1/0 86/87 1 0 0 0 1 1 1 1/0 8e/8f the registers of the vpx have 8 or 16-bit data size; 16-bit registers are accessed by reading/writing two 8-bit data bytes with the high byte first. the order of the bits in a data/address/subaddress byte is always msb first. write to hardware control registers s 1 0 0 0 0 1 1 0 ack sub-addr ack send data-byte ack p read from hardware control registers s 1 0 0 0 0 1 1 0 ack sub-addr ack s 1 0 0 0 0 1 1 1 ack receive data-byte nak p note: s = i 2 c-bus start condition p = i 2 c-bus stop condition ack = acknowledge-bit (active low on sda from receiving device) nak = no acknowledge-bit (inactive high on sda from receiving device) before accessing the address or data registers for the fp interface (fprd, fpwr, fpdat), make sure that the busy bit of fp is cleared (fpsta).
preliminary data sheet vpx 3220 a, vpx 3216 b, vpx 3214 c micronas intermetall 28 figure 41 shows i 2 c bus protocols for read and write operations of the interface. the read operation requires an extra start condition after the subaddress and repeti- tion of the read chip address, followed by the read data bytes. the following protocol examples use device ad- dress hex 86/87. fig. 41: i 2 c bus protocol (msb first) sda scl 1 0 sp 4.5. fp control and status registers in addition to the i 2 c subaddress space, a second class of address space is defined for direct communication with the on-board m- controller. these registers are ac- cessed via indirect addressing through i 2 c registers (see fig. 42). due to the internal architecture of the vpx 3220 a, the ic cannot react immediately to all i 2 c requests which in- teract with the embedded processor (fp). the maxi- mum response timing is approx. 20 ms (one tv field) for the fp processor if tv standard switching is active. if the addressed processor is not ready for further transmis- sions on the i 2 c bus, the clock line scl is pulled low. this puts the current transmission into a wait state. after a certain period of time, the vpx releases the clock and the interrupted transmission is carried on. fp m controller 0 ff read address write address data status 0 ff i 2 c subaddress space fp subaddress space fig. 42: fp register addressing write to fp s 1 0 0 0 0 1 1 0 ack fpwr ack send fp-address- byte high ack send fp-address- byte low ack p s 1 0 0 0 0 1 1 0 ack fpdat ack send data-byte high ack send data-byte low ack p read from fp s 1 0 0 0 0 1 1 0 ack fprd ack send fp-address- byte high ack send fp-address- byte low ack p s 1 0 0 0 0 1 1 0 ack fpdat ack s 1 0 0 0 0 1 1 1 ack receive data-byte high ack receive data-byte low nak p
vpx 3220 a, vpx 3216 b, vpx 3214 c preliminary data sheet micronas intermetall 29 4.6. i 2 c initialization in order to completely specify the operational mode of the vpx, appropriate values must be loaded into both the i 2 c and fp registers. for both the i 2 c and fp regis- ters, this data is loaded from internal rom. the length of this set-up procedure is approximately 200 m sec after the leading edge of res#. initialization is basically a two step procedure: first, the i 2 c registers are initialized, and afterwards, the fp runs its own initialization routine. there are two different set- ups for the i 2 c initialization available. the selection is made with the pin signal pixclk. on the active inac- tive edge of the res# signal, the state of the pixclk pin is latched and used as an index to the selected rom table. 4.7. i 2 c control and status registers the following tables give definitions for the vpx control and status registers. the number of bits indicated for each register in the table is the number of bits imple- mented in the hardware, i.e. a 9-bit register must always be accessed using two data bytes, but the 7 msb will be don't care on write operations and 0 on read operations. write registers that can be read back are indicated in the following table. a hardware reset initializes all control registers to 0. the automatic chip initialization loads a selected set of val- ues from one of four internal rom tables. the mnemonics used in the intermetall vpx demo soft- ware are given in the last column. i 2 c-register table i 2 c reg. address number of bits mode function name chip identification 00 8 r manufacture id in accordance with jedec solid state products engineering council, washington dc intermetall code ec hex i2c_id0 01 / 02 8 / 8 r 16-bit part number (01: lsbs, 02: msbs) vpx 3220 a 4680 hex vpx 3216 b 4260 hex vpx 3214 c 4280 hex i2c_id1, i2c_id2 fast processor (fp) 26 12 / 16 wd fp read address fprd bit [7:0] : address addr bit [15:8] : reserved (must be set to zero) 27 12 / 16 wd fp write address fpwr bit [7:0] : address addr bit [15:8] : reserved (must be set to zero) registers 26 hex and 27 hex use the same hardware by subaddressing. 28 12 / 16 w fp data fpdat bit [11:0] : data data bit [15:12] : reserved (must be set to zero) 29 3 / 8 r fp status fpsta bit [0] : write request bit [1] : read request bit [2] : busy bit [7:3] : reserved (return ones) the control register modes are w: write/read register r: read-only register d: register is double latched v: register is latched with vsync a: register is available only in vpx 3220 a; vpx 3216 b returns valid ack, although no internal action is performed the mnemonics used in the intermetall vpx demo software are given in the last column.
preliminary data sheet vpx 3220 a, vpx 3216 b, vpx 3214 c micronas intermetall 30 i 2 c-register table name function mode number of bits i 2 c reg. address analog front-end 33 8 w input selector luma adc: bit [1:0] 00 vin3 01 vin2 10 vin1 11 reserved (no luma input selected) afend vis input selector chroma adc: bit [2] 0/1 select vin1/cin cs clamping modes: bit [3] 0/1 clamp on/off for chroma adc dclc bit [5:4] reserved (must be set to zero) bit [6] 1 stand-by luma adc bit [7] 1 stand-by chroma adc href, vref d8 8 w href and vref control refsig bit [0] : reserved (must be set to zero) bit [1] : href polarity 0 active high 1 active low hpol bit [2] : vref polarity 0 active high 1 active low vpol bit [5:3] : vref pulse width. binary value + 2 0 0 0 pulse width = 2 1 1 1 pulse width = 9 vlen bit [6] : pref select 0 odd/even flag 1 pintr (programmable interrupt signal) prefsel bit [7] : pref polarity 0 polarity unchanged 1 invert polarity prefpol chroma processing 20 2 / 8 w if compensation: ifc bit [1:0] 00 12 db 01 reserved 10 6 db/oct 11 0 db/oct bit [7:2] reserved (must be set to zero) the control register modes are w: write/read register r: read-only register d: register is double latched v: register is latched with vsync a: register is available only in vpx 3220 a; vpx 3216 b returns valid ack, although no internal action is performed the mnemonics used in the intermetall vpx demo software are given in the last column.
vpx 3220 a, vpx 3216 b, vpx 3214 c preliminary data sheet micronas intermetall 31 i 2 c-register table name function mode number of bits i 2 c reg. address color space converter e0 8 w alpha keyer: y max (vpx 3220 a and vpx 3216 b) ymax bit [7:0] : y max (integer) ymax e1 8 w alpha keyer: y min (vpx 3220 a and vpx 3216 b) ymin bit [7:0] : y min (integer) ymin e2 8 w alpha keyer: c b max (vpx 3220 a and vpx 3216 b) umax bit [7:0] : c b max (2's complement) umax e3 8 w alpha keyer: c b min (vpx 3220 a and vpx 3216 b) umin bit [7:0] : c b min (2's complement) umin e4 8 w alpha keyer: c r max (vpx 3220 a and vpx 3216 b) vmax bit [7:0] : c r max (2's complement) vmax e5 8 w alpha keyer: c r min (vpx 3220 a and vpx 3216 b) vmin bit [7:0] : c r min (2's complement) vmin e6 8 w contrast brightness 1 cbm_bri bit [7:0] : brightness level (binary offset) brightness e7 8 w contrast brightness 2 cbm_con bit [5:0] : contrast level .... linear scale factor for luminance [5] integer part [4:0] fractional part default = 1.0 contrast bit [7:6] : noise shaping .... control for 10 bit to 8 bit conversion 0 0 : 9-bit to 8-bit via1-bit rounding 0 1 : 9-bit to 8-bit via truncation 1 0 : 9-bit to 8-bit via 1-bit error diffusion 1 1 : 10-bit to 8-bit via 2-bit error diffusion noise the control register modes are w: write/read register r: read-only register d: register is double latched v: register is latched with vsync a: register is available only in vpx 3220 a; vpx 3216 b returns valid ack, although no internal action is performed the mnemonics used in the intermetall vpx demo software are given in the last column.
preliminary data sheet vpx 3220 a, vpx 3216 b, vpx 3214 c micronas intermetall 32 i 2 c-register table name function mode number of bits i 2 c reg. address color space converter e8 8 w format selection, alpha keyer and contrast brightness format bit [7, 5, 2:0] : unused in vpx 3214 c bit [2:0] : format selector: 000 yuv 4:2:2, yuv 4:2:2 itur 001 yuv 4:4:4, 010 yuv 4:1:1 011 yuv 4:1:1 dpcm 100 rgb 888 24 bit 101 rgb 888 (invers gamma) 24 bit 110 rgb 565 (invers gamma) 16 bit 111 rgb 555 (invers gamma) + alpha key 15+1 bit format bit [3] : select data format of c b, c r video output data stream 0 2's complement (128 ... 127) 1 binary offset (0 ... 255) twosq bit [4] : contrast brightness: clamping level 0 clamping level = 32, 1 clamping level = 16 clamp bit [5] : gamma: round dither enable (=1) dither bit [6] : alpha key polarity 0 active high 1 active low bit [6] : programmable output pin in vpx 3214 c, connected to tdo keyinv bit [7] : alpha key median filter 0 median filter is disable 1 median filter is enable median ea 8 w diverse settings bit [2:0] : reserved (must be set to zero). bit [3] : connect llc2 to alpha/tdo pin bit [4] : llc2 polarity bit [5] : 0 output fifo pointer reset with posedge of vact intern 1 output fifo pointer reset with vrf=0. ffres bit [7:6] : reserved (must be set to zero) the control register modes are w: write/read register r: read-only register d: register is double latched v: register is latched with vsync a: register is available only in vpx 3220 a; vpx 3216 b returns valid ack, although no internal action is performed the mnemonics used in the intermetall vpx demo software are given in the last column.
vpx 3220 a, vpx 3216 b, vpx 3214 c preliminary data sheet micronas intermetall 33 i 2 c-register table name function mode number of bits i 2 c reg. address output multiplexer f0 8 w output fifo ofifo fifo control: (only available in asynchronous mode) bit [4:0] : fifo flag half full level (interface signal hf ) hfull bit [7:5] : bus shuffler 000 out[23:0] = in[23:0] 001, 010 out[23:0] = in[7:0, 23:8] 011 out[23:0] = in[15:0, 23:16] 100 out[23:0] = in[15:8, 23:16, 7:0] 101, 110 out[23:0] = in[7:0, 15:8, 23:16] 111 out[23:0] = in[23:16, 7:0, 15:8] meaning: in[23:0] : data from color space stage out[23:0] : data to output fifo shuf f1 8 w output multiplexer omux vact bit [1:0]: port mode 00 parallel_out, 'single clock' port a = fifoout[23:16] port b = fifoout[15:8]; 01 'double clock' (only available with a transport rate of 13.5 mhz) port a = fifoout[23:16] / fifoout[15:8], port b = fifoout[7:0]; 10,11 reserved mode vact bit [2] : asynchronous mode: clock slope (if clock source = external) 1 negative edge triggered 0 positive edge triggered. synchronous mode: data reset 1 set output ports to 0 during vact(/fe#) = 0. slope vact bit [3] : clock source 1 internal source (synchronous mode) pixclk is output 0 external mode (asynchronous mode) pixclk is input clkio direct bit [5:4] : delay signal 'active video' (signal fe ) with respect to video output data. only available in synchronous mode. 00 no delay (default) 01 one clock cycle 10 two clock cycles 11 three clock cycles delay direct bit [6] : 1 disable fifo-empty fe low pass filter only available in asynchronous mode. bit [7] : 1 enable hlen counter hlen the control register modes are w: write/read register r: read-only register d: register is double latched v: register is latched with vsync a: register is available only in vpx 3220 a; vpx 3216 b returns valid ack, although no internal action is performed the mnemonics used in the intermetall vpx demo software are given in the last column.
preliminary data sheet vpx 3220 a, vpx 3216 b, vpx 3214 c micronas intermetall 34 i 2 c-register table name function mode number of bits i 2 c reg. address output multiplexer f2 8 w output enable oena direct bit [0] : 1 enable video port a 0 disable / high impedance mode aen direct bit [1] : 1 enable video port b 0 disable / high impedance mode ben direct bit [2] : reserved (must be set to zero) direct bit [3] : 1 enable controls (href, vref, pref, hf#, fe#, alpha) 0 disable / high impedance mode zen direct bit [4] : 1 enable llc-clock to hf -pad (if transport rate is 13 mhz and internal clock source is used) llcen direct bit [5] : 1 enable fsy-data to hf -pad (if transport rate is 20 mhz and internal clock source is used) fsyen direct bit [6] : 1 synchronize href, vref with pixclk hvsynbyq direct bit [7] : 1 disable oeq pin function f8 6 / 8 w pad driver strength ttl output pads typ a driver_a bit [2:0] : driver strength of port a[7:0] stra1 bit [5:3] : driver strength of pixclk, hf# and fe# stra2 bit [7:6] : additional pixclk driver strength strength = bit [5:3] | {bit [7:6], 0} f9 6 / 8 w pad driver strength ttl output pads typ b driver_b bit [2:0] : driver strength of port b[7:0] and c[7:0] strb1 bit [5:3] : driver strength of href, vref, pref and alpha strb2 bit [7:6] : reserved (must be set to zero) the control register modes are w: write/read register r: read-only register d: register is double latched v: register is latched with vsync a: register is available only in vpx 3220 a; vpx 3216 b returns valid ack, although no internal action is performed the mnemonics used in the intermetall vpx demo software are given in the last column.
preliminary data sheet vpx 3220 a, vpx 216 b, vpx 3214 c micronas intermetall 35 4.8. fp control and status registers the tables below list the registers which are currently defined. electrically, all of the registers in the fp subad- dress space are both readable and writeable. function- ally, they are intended for either read or write (as shown in the `mode' column) warning: the fp subaddress space accesses the ram of the fast processor. it is therefore very sensitive to unintended access. in particular, the user must be sure not to overwrite reserved areas. fp-register table fp reg. address number of bits mode function name load table for window #1 winloadtab1 88 12 w vertical begin bit [8:0] : vertical begin (field line number) minimum line number 7 maximum line number determined by current tv line standard vbeg1 a bit [11:9] sharpness control .... regulates the subjective sharpness by selecting filters to admitting horizontal alias / blurring 1 1 1 maximum blurring 1 1 0 ..... 1 0 1 more blurring 0 0 0 default filter setting 0 0 1 more aliasing 0 1 0 ..... 0 1 1 maximum aliasing 1 0 0 set filters for pass-thru 89 12 w vertical lines in bit [8:0] : number of input lines vlinei1 bit [9] reserved (must be set to zero) bit [11:10] : field flag 1 1 window disabled 1 0 window enabled in odd fields only 0 1 window enabled in even fields only 0 0 window enabled in both fields 8a 12 w vertical lines out bit [8:0] : number of output lines vlineo1 bit [11:9] reserved (must be set to zero) 8b 12 w horizontal begin bit [10:0] : horizontal start of window hbeg1 bit [11] reserved (must be set to zero) 8c 12 w horizontal length bit [10:0] : horizontal length of window hlen1 bit [11] reserved (must be set to zero) 8d 12 w number of pixels bit [10:0] : number of active pixels per line npix1 bit [11] reserved (must be set to zero) the control register modes are w: write/read register r: read-only register a: register or register field has function only in vpx 3220 a the mnemonics used in the intermetall vpx demo software are given in the last column.
preliminary data sheet vpx 3220 a, vpx 3216 b, vpx 3214 c micronas intermetall 36 fp-register table fp reg. address number of bits mode function name load table for window #2 winloadtab2 8e 12 w vertical begin bit [8:0] : vertical begin (field line number) minimum line number 7 maximum line number determined by current tv line standard vbeg2 a bit [11:9] sharpness control ...regulates the subjective sharpness by selecting filters to admitting horizontal alias / blurring 1 1 1 maximum blurring 1 1 0 ..... 1 0 1 more blurring 0 0 0 default filter setting 0 0 1 more aliasing 0 1 0 ..... 0 1 1 maximum aliasing 1 0 0 set filters for pass-thru 8f 12 w vertical lines in bit [8:0] : number of input lines vlinei2 bit [9] reserved (must be set to zero) bit [11:10] : field flag 1 1 window disabled 1 0 window enabled in odd fields only 0 1 window enabled in even fields only 0 0 window enabled in both fields 90 12 w vertical lines out bit [8:0] : number of output lines vlineo2 bit [11:9] reserved (must be set to zero) 91 12 w horizontal begin bit [10:0] : horizontal start of window hbeg2 bit [11] reserved (must be set to zero) 92 12 w horizontal length bit [10:0] : horizontal length of window hlen2 bit [11] reserved (must be set to zero) 93 12 w number of pixels bit [10:0] : number of active pixels per line npix2 bit [11] reserved (must be set to zero) the control register modes are w: write/read register r: read-only register a: register or register field has function only in vpx 3220 a the mnemonics used in the intermetall vpx demo software are given in the last column.
preliminary data sheet vpx 3220 a, vpx 216 b, vpx 3214 c micronas intermetall 37 fp-register table fp reg. address number of bits mode function name control word f0 12 w r register for control and latching cmdwd w bit [0] : transport rate 0 20.25 mhz. 1 13.5 mhz. settr w bit [1] : latch transport rate 1 latch (reset automatically) lattr w bit [3:2] : sync timing mode 0 0 open 0 1 forced 1 x scan settm w bit [4] : latch timing mode 1 latch (reset automatically) lattm w bit [5] : latch window #1 1 latch (reset automatically) latwin1 w bit [6] : latch window #2 1 latch (reset automatically) latwin2 wr bit[8] : odd/even mode 0 toggles always 1 follows odd/even property of input video signal disoef bit [11:9] reserved (must be set to zero) info word infoword f1 12 r internal status register do not overwrite bit [2:0] : reserved bit [5:3] : current active tv standard x x x see table of 3-bit code of tv standards acttv bit [6] : line standard of currently active tv standard 0 525 / 60 1 625 / 50 actls bit [11:7] reserved the control register modes are w: write/read register r: read-only register a: register or register field has function only in vpx 3220 a the mnemonics used in the intermetall vpx demo software are given in the last column.
preliminary data sheet vpx 3220 a, vpx 3216 b, vpx 3214 c micronas intermetall 38 the fp ram locations which manage the tv coding standard (selection/recognition) all use a 3-bit code for the eight supported standards. this code (shown below) is assumed in the register descriptions which follow. 0 0 0 pal b,g,h,i (625/50) 0 0 1 ntsc m (525/60) 0 1 0 secam (625/50) 0 1 1 ntsc 44 (525/60) 1 0 0 pal m (525/60) 1 0 1 pal n (625/50) 1 1 0 pal 60 (525/60) 1 1 1 ntsc comb (525/60) fp-register table fp reg. address number of bits mode function name tv standard write tvstndwr f2 12 w writeable control register for managing the tv coding standard bit [0] : manual / automatic select 0 automatic 1 manual mansel bit [3:1] : tv standard for manual selection x x x see table above settv bit [4] : latch the tv standard manually 1 latch (reset automatically) lattv bit [5] : composite / s-vhs select 0 composite 1 s-vhs svhssel bit [9:6] : threshold for standard search results 1 1 1 1 perfect score (maximum score) 0 0 0 0 'no video' (minimum score) 1 1 1 1 default score bit [11:10] reserved (must be set to zero) the control register modes are w: write/read register r: read-only register a: register or register field has function only in vpx 3220 a the mnemonics used in the intermetall vpx demo software are given in the last column.
preliminary data sheet vpx 3220 a, vpx 216 b, vpx 3214 c micronas intermetall 39 fp-register table fp reg. address number of bits mode function name tv standard read tvstndrd f3 12 r readable control register for managing the tv coding standard bit [0] : vact suppress 0 enabled 1 suppressed bit [1] : status of recognition routine 0 idle 1 running bit [4:2] : tv standard detected (by recognition routines) x x x see table above bit [5] : 'no video' flag 0 tv standard shown in bit [4:2] present 1 no video at selected input bit [9:6] : high score from video recognition routine (confidence level) 1 1 1 1 maximum confidence 0 0 0 0 minimum confidence bit [10] : tv line standard (for tv standard from bit [4:2] above) 0 525/60 1 625/50 bit [11] : reserved vertical standard e7 12 w writeable control register for vertical locking vsdt bit [0]: vertical standard lock enable 0 disabled 1 enabled bit [11:1] expected number of lines per field color processing 1c ntsc tint angle, 512 = p /4 tint a0 acc reference; also used to control color saturation accref = 0: acc turned off accref = 1: minimal color saturation ie. color switched off accref a3 acc multiplier value for secam dr chroma component to adjust c r level accr a4 acc multiplier value for secam db chroma component to adjust c b level accb a8 amplitude color killer level kilvl = 0: killer disabled kilvl the control register modes are w: write/read register r: read-only register a: register or register field has function only in vpx 3220 a the mnemonics used in the intermetall vpx demo software are given in the last column.
preliminary data sheet vpx 3220 a, vpx 3216 b, vpx 3214 c micronas intermetall 40 fp-register table fp reg. address number of bits mode function name automatic gain control b2 12 w sync amplitude reference agcref = 0: agc disabled write 0 to fp register b5 after writing 0 to agcref to disable the agc agcref be 12 w start value for agc gain while vertical lock or agc is inactive sgain 20 12 r agc gain value gain dvco 58 12 w crystal oscillator center frequency adjust, 2048..2047 dvco 59 12 r crystal oscillator center frequency adjustment value for line lock mode. true adjust value is dvco adjust. for factory crystal alignment: set dvco=0, set lock mode, read crystal offset from adjust register and use negative value for initial center frequency adjustment via dvco. adjust 26 12 w line locked mode lock command/status xlg write: 100 enable lock 0 disable lock read: 4095/0 locked / unlocked horizontal pll 4b 12 w gain of the horizontal pll bit [4:0] gain for the integrating part of pll control if1 bit [9:5] gain for the proportional part of pll control if2 bit [11:10] reserved the control register modes are w: write/read register r: read-only register a: register or register field has function only in vpx 3220 a the mnemonics used in the intermetall vpx demo software are given in the last column.
preliminary data sheet vpx 3220 a, vpx 216 b, vpx 3214 c micronas intermetall 41 4.9. initial values on reset pixclk low on reset table of initial values type name address data description i 2 c ofifo f0 0a half full level to 0a hex (10 dec ), bus shuffler off i 2 c afend 33 0d video input 2, chroma adc from chroma input, clamp off for chroma adc i 2 c ifc 20 03 if compensation 0 db/oct i 2 c ymax e0 ff open up all comparators, so that alpha key is always true (set) i 2 c ymin e1 00 i 2 c umax e2 7f i 2 c umin e3 80 i 2 c vmax e4 7f i 2 c vmin e5 80 i 2 c cbm_bri e6 00 brightness to 0 i 2 c cbm_con e7 20 contrast to 1.0, noise shaping 9 to 8 bit via 1 bit rounding i 2 c format e8 f8 yuv 422, c r ,c b in binary offset, con/bri clamp to 16 dec , gamma dither enabled, alpha active low, alpha median filter enabled i 2 c omux f1 00 single clock, pixclk input, posedge triggered, hlen counter disabled i 2 c driver_a f8 12 port a, pixclk, hf# and fe# strength to 2 i 2 c driver_b f9 24 port b, href, vref, pref and alpha strength to 4 i 2 c oena f2 00 all outputs disabled pixclk high on reset i 2 c ofifo f0 0b half full level to 0b hex (11 dec ), bus shuffler off i 2 c afend 33 0d video input 2, chroma adc from chroma input, clamp off for chroma adc i 2 c ifc 20 03 if compensation 0 db/oct i 2 c ymax e0 ff open up all comparators, so that alpha key is always true (set) i 2 c ymin e1 00 i 2 c umax e2 7f i 2 c umin e3 80 i 2 c vmax e4 7f i 2 c vmin e5 80 i 2 c cbm_bri e6 00 brightness to 0 i 2 c cbm_con e7 20 contrast to 1.0, noise shaping 9- to 8-bit via 1-bit rounding i 2 c format e8 f8 yuv 422, c r ,c b in binary offset, con/bri clamp to 16 dec , gamma dither enabled, alpha active low, alpha median filter enabled i 2 c omux f1 08 single clock, pixclk output, hlen counter disabled i 2 c driver_a f8 12 port a, pixclk, hf# and fe# strength to 2 i 2 c driver_b f9 24 port b, href, vref, pref and alpha strength to 4 i 2 c oena f2 5f all outputs enabled: synchronize href, vref with pixclk
preliminary data sheet vpx 3220 a, vpx 3216 b, vpx 3214 c micronas intermetall 42 pixclk low or high on reset table of initial values type name address hex data dec description fp tint 1c 0 neutral tint fp 4b 664 hpll: if1 = 24 if2 = 20 fp dvco 58 0 fp adjust 59 0 fp winloadtab1 88 12 fp 89 1 fp 8a 1 fp 8b 0 fp 8c 704 fp 8d 704 fp winloadtab2 8e 17 fp 8f 500 fp 90 500 fp 91 0 fp 92 704 fp 93 704 fp accref a0 2070 fp kilvl a8 30 fp agcref b2 768 fp sgain be 27 fp vsdt e7 523 fp cmdwd f0 114 transport rate 20.25 mhz, sync timing mode open, both windows latched, vact en- abled fp tvstndwr f2 979 manual tv standard select, composite signal
vpx 3220 a, vpx 3216 b, vpx 3214 c preliminary data sheet micronas intermetall 43 5. jtag boundary-scan, test access port (tap) the design of the test access port, which is used for boundary-scan test conforms to standard ieee 1149.1-1990, with one exception. also included is a list of the mandatory instructions supported, as well as the optional instructions. this is only a brief overview of some of the basics, as well as any optional features which are incorporated. the ieee 1149.1 document may be necessary for a more concise description. final- ly, an adherence section goes through a checklist of top- ics and describes how the design conforms to the stan- dard. the implementation of the instructions highz and clamp conforms to the supplement p1149.1/d11 (oc- tober 1992) to the standard 1149.1-1990. 5.1. general description the tap in the vpx is incorporated using the four signal interface. the interface includes tck, tms, tdi, and tdo. the optional treset signal is not used. this is not needed because the chip has an internal power-on- reset which will automatically steer the chip into the test-logic-reset state. the goal of the interface is to provide a means to test the boundary of the chip. there is no support for internal or bist(built-in self test). the one exception to ieee 1149.1 is that the tdo output is shared with the alpha signal. this was done be- cause of i/o restrictions on the chip (see section 5.3. aexceptions to ieee 1149.1o for more information). 5.2. tap architecture the tap function consists of the following blocks: tap- controller, instruction register, boundary-scan register, bypass register, optional device identification register, and master mode register. 5.2.1. tap controller the tap controller is responsible for responding to the tck and tms signals. it controls the transition between states of this machine. these states control selection of the data or instruction registers and the actions which occur in these registers. these include capture, shifting, and update. see fig. 51 of ieee 1149.1 for tap state diagram. 5.2.2. instruction register the instruction register chooses which one of the data registers is placed between the tdi and tdo pins when the select data register state is entered in the tap con- troller. when the select instruction register state is ac- tive, the instruction register is placed between the tdi and tdo. instructions the following instructions are incorporated: bypass sample/preload extest master mode id code highz clamp 5.2.3. boundary scan register the boundary-scan register (bsr) consists of bound- ary-scan cells (bscs) which are distributed throughout the chip. these cells are located at or near the i/o pad. it allows sampling of inputs, controlling of outputs, and shifting between each cell in a serial fashion to form the bsr. this register is used to verify board interconnect. input cell the input cell is constructed to achieve capture only. this is the minimal cell necessary since internal test (intest) is not supported. the cell captures either the system input in the capture-dr state or the previous cells output in the shift-dr state. the captured data is then available to the next cell. no action is taken in the update-dr state. see figure 1011 of ieee 1149.1 for reference. output cell the output cell will allow both capture and update. the capture flop will obtain system information in the cap- ture-dr state or previous cells information in the shift-dr state. the captured data is available to the next cell. the captured or shifted data is downloaded to the update flop during the update-dr state. the data from the update flop is then multiplexed to the system output pin when the extest instruction is active. other- wise, the normal system path exists where the signal from the system logic flows to the system output pin. see fig. 1012 of ieee 1149.1 for reference.
preliminary data sheet vpx 3220 a, vpx 3216 b, vpx 3214 c micronas intermetall 44 tristate cell each group of output signals which are tristatable is con- trolled by a boundary scan cell (output cell type). this al- lows either the normal system signal or the scanned sig- nal to control the tristate control. in the vpx, there are four such tristate control cells which control groups of output signals (see section aoutput driver tristate con- trolo for further information). bidirect cell the bidirect cell is comprised of an input cell and a tris- tate cell as described in the ieee standard. the signal pixclk is a bidirectional signal. 5.2.4. bypass register this register provides a minimal path between tdi and tdo. this is required for complicated boards where many chips may be connected in serial. 5.2.5. device identification register this is an optional 32-bit register which contains the- intermetall identification code (jedec controlled), part and revision number. this is useful in providing the tester with assurance that the correct part and revision are inserted into a pcb. 5.2.6. master mode data register this is an optional register used to control an 8-bit test register in the chip. this register supports shift and up- date. no capture is supported. this was done so the last word can be shifted out for verification. 5.3. exception to ieee 1149.1 there is one exception to ieee 1149.1. the exception is to paragraphs 3.1.1.c., 3.5.1.b, and 5.2.1.d (test- logic-reset state). because of pin limitations on the chip, a pin is shared for two functions. when the circuit is in the test-logic-reset state, the alpha signal is driven out the tdo/alpha pin. when the circuit leaves the test-logic-reset state, the tdo signal is driven on this line. as long as the circuit is not in the test-logic-reset state, all the rules for application of the tdo signal adhere to the ieee1149.1 spec. since the vpx uses the jtag function as a boundary- scan tool, the vpx does not sacrifice test of this pin since it is verified by exercising jtag function. the designer of the pcb must make careful note of this fact, since he will not be able to scan into chips receiving the alpha signal via the vpx. the pcb designer may want to put this chip at the end of the chain or bring the vpx tdo out separately and not have it feed another chip in a chain. 5.4. ieee 1149.1-1990 spec adherence this section defines the details of the ieee1149.1 de- sign for the vpx. it describes the function as outlined by ieee1149.1, section 12.3.1. the section of that docu- ment is referenced in the description of each function. 5.4.1. instruction register (section 12.3.1.b.i of ieee 1149.1-1990) the instruction register is three bits long. no parity bit is included. the pattern loaded in the instruction register during capture-ir is binary a101o (msb to lsb). the two lsbs are defined by the spec to be a01o (bit 1 and bit 0) while the msb (bit 2) is set to a1o. 5.4.2. public instructions (section 12.3.1.b.ii of ieee 1149.1-1990) a list of the public instructions is as follows: instruction code (msb to lsb) extest 000 sample/preload 001 id code 010 master mode 011 highz 100 clamp 110 bypass 100 111 the extest and sample/preload instructions both apply the boundary scan chain to the serial path. the id code instruction applies the id register to the serial chain. the bypass, the highz, and the clamp instructions apply the bypass register to the serial chain. the master mode instruction is a test data instruction for public use. it provides the ability to control an 8-bit test register in the chip. 5.4.3. self-test operation (section 12.3.1.b.iii of ieee 1149.1-1990). there is no self-test operation included in the vpx design which is accessible via the tap.
vpx 3220 a, vpx 3216 b, vpx 3214 c preliminary data sheet micronas intermetall 45 5.4.4. test data registers (section 12.3.1.b.iv of ieee 1149.1-1990). the vpx includes the use of four test data registers. they are the required bypass and boundary scan regis- ters, the optional id code register and the master mode register. the bypass register is, as defined, a 1-bit register ac- cessed by codes 100 through 111, inclusive. since the design includes the id code register, the bypass register is not placed in the serial path upon power-up or test- logic-reset. the master mode is an 8-bit test register which is used to force the vpx into special test modes. this is reset upon power-on-reset. this register supports shift and update only. it is not recommended to access this regis- ter. the loading of that register can drive the ic into an undefined state. 5.4.5. boundary-scan register (section 12.3.1.b.v of ieee 1149.1-1990) the boundary-scan chain has a length of 38 shift regis- ters. the scan chain order is specified in the section apin connectionso. 5.4.6. device identification register (section 12.3.1.b.vi of ieee 1149.1-1990) the manufacturer's identification code for-inter- metall is a6co (hex) . the general implementation scheme uses only the 7 lsbs and excludes the msb, which is the parity bit. the part number is a4680o (hex) . the version code starts from a1o (hex) and changes with every revision. the version number relates to changes of the chip interface only. 5.4.7. performance (section 12.3.1.b.vii of ieee 1149.1-1990) see section aspecificationo for further information. version part number manufacturer id 31 28 27 12 11 1 0 1 0010010001101000000000001101 00 1 7f the device identification register 87 246800d9
preliminary data sheet vpx 3220 a, vpx 3216 b, vpx 3214 c micronas intermetall 46 tap state transitions select data reg capture dr shift dr exit1 dr pause dr exit2 dr update dr select instr. reg capture ir shift ir exit1 ir pause ir exit2 ir update ir run / idle test-logic-reset tdo active tdo inactive $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $a $b $c $d $e $f 1 0 0 0 0 00 0 00 0 0 0 0 tms=0 tms=0 11 11 11 11 11 11 tms=1 tms=1 1 state code state transitions are dependend on the value of tms, synchronized by tck. tdo could be used as alpha keyer or llc2 clock signal (see pin description).
vpx 3220 a, vpx 3216 b, vpx 3214 c preliminary data sheet micronas intermetall 47 ************************************************************* this is the bsdl for the 44-pin version of the vpxa design. ************************************************************* library ieee; use work.std_1149_1_1990.all; entity vpxa_44 is generic (physical_pin_map:string := oundefinedo); port( define ports tdi,tck,tms: in bit; tdo,href,vref,pref: out bit; a: out bit_vector(7 downto 0); pvdd,pvss: linkage bit; pixclk: inout bit; oeq: in bit; hfq,feq: out bit; b: out bit_vector(7 downto 0); sda,scl: inout bit; vss,xtal2,xtal1,vdd: linkage bit; resq: in bit; avdd,avss,vrt,isgnd: linkage bit; cin,vin1,vin2,vin3: in bit ); attribute pin_map of vpxa_44 : entity is physical_pin_map; constant package_44 : pin_map_string := map pins to signals otdi : 1 o & otck : 2 o & otdo : 3 o & ohref : 4 o & ovref : 5 o & opref : 6 o & oa : (7,8,9,10,14,15,16,17)o & opvdd : 11 o & opixclk : 12 o & opvss : 13 o & ooeq : 18 o & ohfq : 19 o & ofeq : 20 o & ob : (21,22,23,24,25,26,27,28),o & osda : 29 o & oscl : 30 o & ovss : 31 o & oxtal2 : 32 o & oxtal1 : 33 o & ovdd : 34 o & oresq : 35 o & oavdd : 36 o & ocin : 37 o & oavss : 38 o & ovin1 : 39 o & ovin2 : 40 o & ovrt : 41 o & ovin3 : 42 o & oisgnd : 43 o & otms : 44 o ; attribute tap_scan_in of tdi : signal is true; define jtag controls attribute tap_scan_mode of tms : signal is true; attribute tap_scan_out of tdo : signal is true; attribute tap_scan_clock of tck : signal is (10.0e6,both); max frequency and levels tck can be stopped at. attribute instruction_length of vpxa_44: entity is 3; define instr. length attribute instruction_opcode of vpxa_44: entity is oextest (000),o & external test
preliminary data sheet vpx 3220 a, vpx 3216 b, vpx 3214 c micronas intermetall 48 osample (001),o & sample/preload oidcode (010),o & id code omastermode (011),o & master mode (internal test) ohighz (100),o & highz oclampo (110),o & clamp obypass (100,101,110,111),o; bypass attribute register_access of vpxa_44: entity is instr. vs register oboundary (extest,sample),o & control obypass (bypass, highz, clamp),o & oidcode[32] (idcode),o & omastermode[8] (mastermode) o; attribute instruction_capture of vpxa_44: entity is o101o; captured instr. attribute idcode_register of vpxa_44: entity is o0001o & initial rev o0100011010000000o & part numb. 4680 o0000o & 7f count o1101100o & intermetall codeparity o1o; mandatory lsb attribute boundary_cells of vpxa_44: entity is obc_1,bc_4o; -bc_1 for output cell bc_4 for input cell attribute boundary_length of vpxa_44: entity is 38; boundary scan length attribute boundary_register of vpxa_44: entity is boundary scan defin. num cell port function safe ccel disval rslt o 37 (bc_4, vin3, input, x ),o & o 36 (bc_4, vin2, input, x ),o & o 35 (bc_4, vin1, input, x ),o & o 34 (bc_4, cin, input, x ),o & o 33 (bc_4, resq, input, x ),o & o 32 (bc_1, *, internal, x ),o & clock health o 31 (bc_4, scl, input, x ),o & o 30 (bc_1, scl, output3, x, 30, 1, z ),o & open collector o 29 (bc_4, sda, input, x ),o & o 28 (bc_1, sda, output3, x, 28, 1, z ),o & open collector o 27 (bc_1, b(0), output3, x, 19, 1, z ),o & o 26 (bc_1, b(1), output3, x, 19, 1, z ),o & o 25 (bc_1, b(2), output3, x, 19, 1, z ),o & o 24 (bc_1, b(3), output3, x, 19, 1, z ),o & o 23 (bc_1, b(4), output3, x, 19, 1, z ),o & o 22 (bc_1, b(5), output3, x, 19, 1, z ),o & o 21 (bc_1, b(6), output3, x, 19, 1, z ),o & o 20 (bc_1, b(7), output3, x, 19, 1, z ),o & o 19 (bc_1, *, control, x ),o & control o 18 (bc_1, feq, output3, x, 16, 1, z ),o & o 17 (bc_1, hfq, output3, x, 16, 1, z ),o & o 16 (bc_1, *, control, x ),o & control o 15 (bc_4, oeq, input, x ),o & o 14 (bc_1, a(0), output3, x, 7, 1, z ),o & o 13 (bc_1, a(1), output3, x, 7, 1, z ),o & o 12 (bc_1, a(2), output3, x, 7, 1, z ),o & o 11 (bc_1, a(3), output3, x, 7, 1, z ),o & o 10 (bc_1, clkio, control, x ),o & o 9 (bc_4, pixclk,input, x ),o & o 8 (bc_1, pixclk,output3, x, 10, 1, z ),o & bidirect o 7 (bc_1, *, control, x ),o & control o 6 (bc_1, a(4), output3, x, 7, 1, z ),o & o 5 (bc_1, a(5), output3, x, 7, 1, z ),o & o 4 (bc_1, a(6), output3, x, 7, 1, z ),o & o 3 (bc_1, a(7), output3, x, 7, 1, z ),o & o 2 (bc_1, pref, output3, x, 16, 1, z ),o & o 1 (bc_1, vref, output3, x, 16, 1, z ),o & o 0 (bc_1, href, output3, x, 16, 1, z ),o; end vpxa_44;
vpx 3220 a, vpx 3216 b, vpx 3214 c preliminary data sheet micronas intermetall 49 6. specification 6.1. outline dimensions 16.5 0.1 4.75 0.15 0.457 10 x 1.27 = 12.7 0.1 10 x 1.27 = 12.7 0.1 1.2 x 45 2.35 2.35 17.4 +0.25 140 39 29 28 18 17 7 6 1.6 1.9 1.5 4.05 16.5 0.1 0.1 17.4 +0.25 5 8.6 6 2 2 x 45 1 +0.2 1.27 0.1 1.27 0.1 fig. 61: 44-pin plastic leaded chip carrier package (plcc44) weight approximately 2.5 g dimensions in mm 0.711 0.254 0.05 fig. 62: 44-pin plastic thin-quad-flat-pack spgs1234/1 (ptqfp44f) weight approximately 0.35 g dimensions in mm 0.8 0.05 1 11 12 22 23 33 34 44 max. 1.6 1.4 0.05 12 0.25 12 0.25 10 0.1 10 0.1 0.8 0.1 10 x 0.8 = 8 0.1 0.05 10 x 0.8 = 8 0.1
preliminary data sheet vpx 3220 a, vpx 3216 b, vpx 3214 c micronas intermetall 50 6.2. pin connections and short descriptions nc = not connected; leave vacant lv = if not used, leave vacant s.t.b. = shorted to bagndi if not used dvss = if not used, connect to dvss x = obligatory; connect as described in circuit diagram ahvss = connect to ahvss pin no. connection pin name type short description plcc 44-pin ptqfp 44-pin (if not used) 1 39 nc tdi in boundary-scan-test data input 2 40 nc tck in (+pull- up) boundary-scan-test clock input 3 41 nc tdo alpha llc2 out out out boundary-scan-test data output if tap is active (see remarks on boundary-scan test) if test access port (tap) is in test-logic- reset state: alpha key signal (i 2 c reg. ea hex bit[3] = 0) if test access port (tap) is in test-logic- reset state: llc/2 = 13 mhz clock signal (i 2 c reg. ea hex bit[3] = 1) 4 42 nc href out horizontal reference 5 43 nc vref out vertical reference 6 44 nc pref odd/even i 2 c-addr out out in programmable interrupt odd/even frame identifier i 2 c-initialization control by positive edge of res : pref = 0 : i 2 c device address 0 pref = 1 : i 2 c device address 1 (for more information see i 2 c description) 7 1 nc a7 out port 1 video data output 8 2 nc a6 out port 1 video data output 9 3 nc a5 out port 1 video data output 10 4 nc a4 out port 1 video data output 11 5 pvdd supply supply voltage pad circuits 12 6 nc pixclk i 2 c-init out in in pixel clock i/o synchronous mode asynchronous mode i 2 c-initialization control by positive edge of res : pixclk = 0 : i 2 c rom table 0 pixclk = 1 : i 2 c rom table 1 (for more information see i 2 c description) 13 7 pvss supply supply voltage pad circuits
vpx 3220 a, vpx 3216 b, vpx 3214 c preliminary data sheet micronas intermetall 51 pin connections and short descriptions, continued pin no. connection pin name type short description plcc 44-pin ptqfp 44-pin (if not used) 14 8 nc a3 out port 1 video data output 15 9 nc a2 out port 1 video data output 16 10 nc a1 out port 1 video data output 17 11 nc a0 out port 1 video data output 18 12 vss oe in output ports enable 19 13 nc hf fsy llc out out out asynchronous mode: fifo half full, active low synchronous mode (20.25 mhz): front sync synchronous mode (13.5 mhz): 2 x pixclk = 27 mhz 20 14 nc fe vact out out asynchronous mode: fifo empty, active low synchronous mode: active video 21 15 nc b7 out port 2 video data output 22 16 nc b6 out port 2 video data output 23 17 nc b5 out port 2 video data output 24 18 nc b4 out port 2 video data output 25 19 nc b3 out port 2 video data output 26 20 nc b2 out port 2 video data output 27 21 nc b1 out port 2 video data output 28 22 nc b0 out port 2 video data output 29 23 nc sda out (pull- down/in) i 2 c data 30 24 nc scl out (pull- down/in) i 2 c clock 31 25 res in reset input 32 26 vss supply supply voltage for digital circuitry 33 27 vdd supply supply voltage for digital circuitry 34 28 xtal2 osc out crystal 35 29 xtal1 osc in crystal 36 30 avdd supply supply voltage for analog circuitry 37 31 nc cin ain chroma input (svhs) 38 32 avss supply supply voltage for analog circuitry
preliminary data sheet vpx 3220 a, vpx 3216 b, vpx 3214 c micronas intermetall 52 short description type pin name connection pin no. (if not used) ptqfp 44-pin plcc 44-pin 39 33 nc vin1 ain video 1 or luminance (svhs) input 40 34 nc vin2 ain video 2 input 41 35 vrt reference reference voltage top (adc) 42 36 nc vin3 ain video 3 input 43 37 isgnd supply signal ground 44 38 nc tms in (pull-up) boundary-scan-test mode select
vpx 3220 a, vpx 3216 b, vpx 3214 c preliminary data sheet micronas intermetall 53 6.3. pin descriptions (pin numbers for plcc44) pins 44, 1 jtag input pins tms, tdi (fig. 66) mode select and data input signal for the jtag test ac- cess port (tap). these inputs have small pull-ups and input stages with schmitt trigger characteristics. pin 2 jtag input pin tck (fig. 65) clock input pin for jtag test access port (tap). this in- put has an input stage with schmitt trigger characteris- tics and no pull-up. pin 3 jtag output pin tdo (fig. 68) data output for jtag test access port (tap), and output pin for the alpha key signal, if the tap is in test-logic- reset state. the output circuit belongs to the character- istics of ttl output driver type b. pins 4 to 6 reference signals href, vref, and pref (fig. 68) these signals are internally generated sync signals. their output characteristics belong to the output driver type b. pins 7 to 10, 14 to 17 video port a (fig. 68) the output characteristics of these pins belong to the characteristics of output driver type a. pin 11 supply voltage, pad circuitry pvdd pin 12 pixel clock pixclk (fig. 69) this signal is either input or output depending on the se- lected mode. in synchronous mode it has the character- istics of ttl output driver type a. in asynchronous mode it has ttl schmitt trigger input characteristics. pixclk is the reference clock for the video data transmission ports a[7:0] and b[7:0]. moreover, the state of the pixclk signal at the inactive going edge of res deter- mines which i 2 c_init table will be loaded (see section 4.9.) pin 13 ground, pad circuitry pvss pin 18 output enable input signal (fig. 65) the output enable input signal has ttl schmitt trigger input characteristics. it controls the tristate condition of both video ports. pins 19, 20 hf , fe , (fig. 68) these pins have different functionality depending on which video data output mode is selected. the output circuits belong to the characteristics of ttl output driver type a. pins 21 to 28 video port b (fig. 68) the output characteristics of these pins belong to the characteristics of ttl output driver type b. pin 29 i 2 c data sda (fig. 67) this pin connects to the i 2 c-bus data line. pin 30 i 2 c clock scl (fig. 67) this pin connects to the i 2 c-bus clock line. pin 31 reset input res (fig. 65) a low level on this pin resets the circuit. pin 32 ground, digital circuitry vss pin 33 supply voltage, digital circuitry vdd pins 34, 35 xtal1 crystal input and xtal2 crystal output (fig. 611) these pins are connected to a 20.25 mhz crystal oscilla- tor which is digitally tuned by integrated shunt capaci- tances. an external clock can be fed into xtal1. in this case clock frequency adjustment must be switched off. pin 36 supply voltage, analog circuitry avdd pin 37 chroma input cin (fig. 610, fig. 614) this pin is connected to the s-vhs chroma signal. a re- sistive divider is used to bias the input signal to the middle of the converter input range. cin can only be connected to the chroma (video 2) ad converter. the signal must be ac-coupled. pin 38 ground, analog front-end avss pins 39, 40, 42 video input 13 vin1,vin2,vin3 (fig. 612) these are the analog video inputs. a cvbs, s-vhs luma signal is converted using the luma (video 1) ad converter. the vin1 input can also be switched to the chroma (video 2) adc. the input signal must be ac- coupled. pin 41 reference voltage top vrt (fig. 613) via this pin, the reference voltage for the ad converters is decoupled. the pin is connected with 10 m f/47 nf to the signal ground pin. pin 43 signal ground for analog input isgnd this is the high-quality ground reference for the video input signals.
preliminary data sheet vpx 3220 a, vpx 3216 b, vpx 3214 c micronas intermetall 54 6.4. pin configuration 7 8 9 10 11 12 13 14 15 16 17 29 30 31 32 33 34 35 36 37 38 39 18 19 20 21 22 23 24 25 26 27 28 6 5 4 3 2 1 4443424140 vpx 3220 a, top view fig. 63: 44-pin plcc package. vin1 avss cin avdd xtal1 xtal2 vdd vss res scl sda b0 b1 b2 b3 b4 b5 vin2 vrt vin3 isgnd tms tdi tck tdo (alpha, llc2) href vref pvss a2 a1 a0 a3 pixclk pvdd a4 a5 a6 a7 pref (odd/even) oe hf (fsy, llc) fe (vact) b7 b6 vpx 3216 b fig. 64: 44-pin ptqfp package. 1 2 3 4 5 6 7 8 9 10 11 23 24 25 26 27 28 29 30 31 32 33 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 vpx 3220 a, top view vin1 avss cin avdd xtal1 xtal2 vdd vss res scl sda b0 b1 b2 b3 b4 b5 vrt vin3 isgnd tms tdi tck href vref pvss a2 a1 a7 oe hf (fsy, llc) fe (vact) b7 b6 tdo (alpha, llc2) vin2 pref (odd/even) a6 a5 a4 pvdd pixclk a3 a0 vpx 3216 b
vpx 3220 a, vpx 3216 b, vpx 3214 c preliminary data sheet micronas intermetall 55 6.5. pin circuits fig. 65: tck, oe , res in fig. 66: jtag inputs tms, tdi p on pvdd p fig. 67: i 2 c interface sda, scl pin the characteristics of the schmitt triggers are dependent of the supply of vdd/vss. p n pvdd pvss fig. 68: a[7:0], b[7:0], href, vref, pref, hf , fe , tdo out p n pvdd pvss fig. 69: input/output pixclk in / out vrt fig. 610: unselected video inputs off vin1, vin2, vin3, cin
preliminary data sheet vpx 3220 a, vpx 3216 b, vpx 3214 c micronas intermetall 56 avdd avss p n 0.5m fig. 611: crystal oscillator xtal2 xtal1 f eclk avdd avss to adc1 fig. 612: video inputs adc1 vin1 n n n vin2 vin3 clamping avss avdd p + bias adc reference fig. 613: reference voltage vrt pin avdd avss to adc2 fig. 614: video inputs adc2 vin1 n n cin clamping to adc2 vin1 n n cin avdd avss bias clamping or bias is selectable via i 2 c reg. 33 hex bit[3]
vpx 3220 a, vpx 3216 b, vpx 3214 c preliminary data sheet micronas intermetall 57 6.6. electrical characteristics 6.6.1. absolute maximum ratings symbol parameter pin name min. max. unit t a ambient temperature 0 65 c t s storage temperature 40 125 c t j junction temperature 0 125 c v sub supply voltage, all supply inputs 0.3 6 v input voltage of pixclk, tms, tdi pvss 0.5 pvdd + 0.5 1) v input voltage tck pvss 0.5 6 v input voltage sda, scl vss 0.5 6 v signal swing a[7:0], b[7:0], pixclk, href, vref, pref, hf , fe , tdo pvss 0.5 pvdd + 0.5 1) v maximum d | vdd avdd | 0.5 v maximum d | vss pvss | maximum d | vss avss | maximum d | pvss avss | 0.1 v 1) note: external voltage exceeding pvdd+0.5v should not be applied to these pins even when they are three-stated. stresses beyond those listed in the aabsolute maximum ratingso may cause permanent damage to the device. this is a stress rating only. functional operation of the device at these or any other conditions beyond those indicated in the arecommended operating conditions/characteristicso of this specification is not implied. exposure to absolute maxi- mum ratings conditions for extended periods may affect device reliability.
preliminary data sheet vpx 3220 a, vpx 3216 b, vpx 3214 c micronas intermetall 58 limitations due to package characteristics (test conditions at t a = 65 c and t j = 125 c) symbol parameter min. typ. max. unit test conditions r thjc thermal resistance junction-case of ptqfp44 5 k/w r tha thermal resistance ambient of ptqfp44 68 k/w still air p max maximum power radiation of ptqfp44 due to the thermal resistance of the pack- age 890 mw still air, no cooling r thjc thermal resistance junction-case of plcc44 without internal heat sink 11 k/w r tha thermal resistance ambient (still air) of plcc44 without internal heat sink 55 k/w p max maximum power radiation of plcc44 without internal heat sink due to the ther- mal resistance of the package 1089 mw still air, no cooling r thjc thermal resistance junction-case of plcc44 with internal heat sink 8 k/w r tha thermal resistance ambient (still air) of plcc44 with internal heat sink 44 k/w p max maximum power radiation of plcc44 with internal heat sink due to the thermal resis- tance of the package 1370 mw still air, no cooling
vpx 3220 a, vpx 3216 b, vpx 3214 c preliminary data sheet micronas intermetall 59 6.6.2. recommended operating conditions symbol parameter pin name min. typ. max. unit asup analog supply voltage avdd 4.75 5.0 5.25 v dsup digital supply voltage vdd 4.75 5.0 5.25 v psup pad supply voltage pvdd 3.0 3.3 3.6 v f osc clock frequency xtal1, xtal2 20.25 mhz 6.6.3. power consumption symbol parameter min. typ. max. unit test conditions i dd supply current vpx 3220 a between vdd and vss 115 135 155 ma between avdd and avss 35 44 53 ma between pvdd and pvss application dependent ma i dd supply current vpx 3216 b between vdd and vss 86 ma between avdd and avss 35 44 53 ma between pvdd and pvss application dependent ma the diagrams below illustrate some of the possible output modes and their impact on the power consumption. these values are worst case numbers in terms of number of active output drivers. only the video data interface a[7:0] and b[7:0], and the clock signals pixclk have to be considered. as a first order approximation, the remaining signals have no impact on the power consumption. 0.9 1.0 1.1 1.2 1.3 1.4 10 20 30 40 50 60 70 80 total power consumptioin [w] cload [pf] pvdd = 5.0 v pvdd = 3.3 v based on a worst case scenario of 18 active output pins, no static loads, and a typical power consumption. 13mhz 20mhz 27mhz 13mhz 20mhz 27mhz 0.6 0.7 0.8 0.9 1.0 1.1 10 20 30 40 50 60 70 80 pvdd = 5.0 v pvdd = 3.3 v vpx 3220 a vpx 3216 b total power consumptioin [w] cload [pf] 13mhz 20mhz 27mhz 13mhz 20mhz 27mhz 1370 mw: plcc + heatsink 1089 mw: plcc 1089 mw: plcc 890 mw: tqfp
preliminary data sheet vpx 3220 a, vpx 3216 b, vpx 3214 c micronas intermetall 60 6.6.4. characteristics, reset at t a = 0 to 65 c, v sup = 4.75 to 5.25 v, f = 20.25 mhz for min./max. values at t c = 60 c, v sup = 5 v, f = 20.25 mhz for typical values symbol parameter min. typ. max. unit test conditions t res ext external reset hold time 50 ns t res int internal reset hold time 3.2 m s xtal osc. is working t res int2 internal register setup after reset (i 2 c ini- tialization) 200 m s 6.6.5. input characteristics of res and oe symbol parameter min. typ. max. unit test conditions v il input voltage low 0.5 0.8 v v ih input voltage high 2.0 6 v v trhl trigger level at transition high to low 1.2 v v trlh trigger level at transition low to high 1.6 v 6.6.6. recommended crystal characteristics symbol parameter min. typ. max. unit test conditions t a operating ambient temperature 0 65 c f p resonance frequency 20.250 mhz c l = 13 pf, t a = 25 c d f p /f p accuracy of adjustment 20 ppm t a = 25 c d f p /f p frequency temperature drift 30 ppm over operating temperature range with respect to fre- quency at 25 c c 0 shunt capacitance 3 7 pf c 1 motional capacitance 18 ff r r series resistance 30 w 6.6.7. xtal input characteristics symbol parameter min. typ. max. unit test conditions v i clock input voltage, xtal1 1.3 v pp capacitive coupling of xtal1, xtal2 open
vpx 3220 a, vpx 3216 b, vpx 3214 c preliminary data sheet micronas intermetall 61 6.6.8. characteristics, analog video inputs symbol parameter pin name min. typ. max. unit test conditions v vin analog input voltage vin1 vin2 vin3 0 2.5 v c in input capacitance vin3 cin 13 pf v in = 1.5 v c cp input coupling capacitor video inputs vin13 680 nf c cp input coupling capacitor chroma input cin 1 nf
preliminary data sheet vpx 3220 a, vpx 3216 b, vpx 3214 c micronas intermetall 62 6.6.9. characteristics, analog front-end and adcs symbol parameter pin name min. typ. max. unit test conditions v vin full scale input voltage, video 1 vin1, vin2 1.8 2.0 2.2 v pp min. agc gain v vin full scale input voltage, video 1 vin2 , vin3 0.5 0.6 0.7 v pp max. agc gain v vincl video 1 input clamping level, cvbs 1.0 v binary level = 68 lsb min. agc gain v cin full scale input voltage, chroma cin, vin1 1.08 1.2 1.32 v pp v vincl video 2 input clamping level, cvbs vin1 1.2 v binary level = 68 lsb v cinb video 2 input bias level, svhs chroma 1.5 v r cin video 2 input resistance svhs chroma 1.4 2 2.6 k w binary code for open chroma input vin1 cin 128 q cl input clamping current resolution vin13, cin 16 15 steps i cl input clamping current per step 0.7 1 1.3 m a v vrt reference voltage top vrt 2.5 2.6 2.8 v 10 m f/10 nf, 1 g w probe bw video 1 bandwidth 10 mhz 3 db for full-scale signal bw video 2 bandwidth 10 mhz 3 db for full-scale signal xtalk crosstalk, any two video inputs 56 db at 1 mhz thd distortion 50 42 db at 1 mhz, 5th harmonics sndr video signal to noise and distortion ratio vin13, cin 41 45 db at 1 mhz, only one output inl video integral non-linearity, static 1 lsb code density dnl video differential non-linearity 0.5 0.8 lsb code density dg video differential gain 3 % 300 mv pp , 4.4 mhz on ramp dp video differential phase 3 deg 300 mv pp , 4.4 mhz on ramp 38 39 40 41 42 43 44 45 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 snr [db] pvdd [v] dependency between snr and power supply both adcs are working and routed to a[7:0], and b[7:0]. all interfaces are working with maximum driver strength bandwidth measurement is performed up to 5 mhz.
vpx 3220 a, vpx 3216 b, vpx 3214 c preliminary data sheet micronas intermetall 63 6.6.10. characteristics of the jtag interface tck clock signal of the test-access port. it is used to syn- chronize all jtag functions. when jtag operations are not being performed, this pin should be driven to vss. the input stage of the tck uses a ttl schmitt trigger. tms, tdi test mode selection and test data input. both signals are inputs with a ttl compatible input specification. to comply with jtag specification they use pull-ups at their input stage. the input stage of the tms and tdi uses a ttl schmitt trigger. tdo test data output. this signal is multiplexed with the function alpha. the output specification conforms to the specification of the ttl output driver type b. tdo 50 pf i = 4 ma 800 w 800 w fig. 615: tdo test circuit symbol parameter min. typ. max. unit test conditions v ol output voltage low 0.6 v v oh output voltage high 2.4 pvdd v a special vdd, vss supply is used only to support the digital output pins. this means inherently that in case of tristate condi tions, external sources should not drive these signals above the voltage pvdd which supplies the output pins. v il input voltage low 0.5 0.8 v v ih input voltage high for input pin tck 2.0 6 v v ih input voltage high for input pin tdi, tms 2.0 pvdd + 0.3 v f cycl jtag cycle time 100 ns f h tck high time 50 ns f l tck low time 50 ns c i input capacitance of pins tck pf of pins tdi and tms pf c o output capacitance (pin tdo) pf i ih input pull-up current (pins tdi and tms) ma v i = v ss i i input leakage current (pin tck) m a v ss v i v dd i o output leakage current (pin tdo) m a tap controller is in test- reset state schmitt trigger hysteresis this specification defines the schmitt trigger hysteresis of the inputs tck, tms, and tdi. v trhl trigger level at transition high to low 1.2 v v trlh trigger level at transition low to high 1.6 v
preliminary data sheet vpx 3220 a, vpx 3216 b, vpx 3214 c micronas intermetall 64 6.6.10.1. timing of the test access port tap t off t on f cycl f h f l t h t s t d tck tdi, tms tdo fig. 616: timing of test access port tap symbol parameter min. typ. max. unit test conditions t s tms, tdi setup time 3 ns t h tms, tdi hold time 3 4 4 ns t d tck to tdo propagation delay for valid data 35 40 45 ns t on tdo turn-on delay 35 40 45 ns t off tdo turn-off delay 35 40 45 ns
vpx 3220 a, vpx 3216 b, vpx 3214 c preliminary data sheet micronas intermetall 65 6.6.11. characteristics, i 2 c bus interface symbol parameter pin name min. typ. max. unit test conditions v itf input trigger level high to low sda, scl 1.5 0.3*vdd 2.0 v v itr input trigger level low to high 2.5 0.6*vdd 3.0 v v ith input trigger hysteresis 0.5 v v ol output low voltage 0.4 0.6 v v i l = 3 ma i l = 6 ma v ih input capacitance 20 pf i l input leakage current 1 1 m a v ss v i v dd t f signal fall time 300 ns c l =400 pf t r signal rise time 1000 ns f scl clock frequency scl 0 400 khz t s setup time pref to res pref 10 ns t h hold time pref to res 10 ns the state of pref and pixclk pins are sampled at the high (inactive) going edge of res in order to determine two power-on parameters (see fig. 617). pref determines the i 2 c address: pref=0: address 1000 011 bin pref=1: address 1000 111 bin pixlck determines the internal rom table which is used to initialize some of i 2 c and fp registers (see sec- tion 4.9.) res pref v ioh v iol v ioh v iol fig. 617: i 2 c selection: slave address (pref) and init table (pixclk) t s t h pixclk v ioh v iol t s t h +0:0
preliminary data sheet vpx 3220 a, vpx 3216 b, vpx 3214 c micronas intermetall 66 6.6.12. digital video interface the following timing specifications refer to the timing diagrams of sections 6.6.12.1., 6.6.12.2., 6.6.12.3., and 6.6.12.4. for pin driver specific values (driver types a and b) see 6.6.13. symbol parameter min. typ. max. unit test conditions oe : see 6.6.5. pixclk: synchronous mode t clk13 cycle time at 13.5 mhz internal data rate 74 ns t clk20 cycle time at 20.25 mhz internal data rate 49.4 ns k pixclk duty cycle f h / (f l + f h ) 50 % t h2 output signal hold time for a [7:0] 15 16 18 ns b [7:0] 16 17 19 ns alpha 16 17 19 ns t h3 output signal hold time of vact 3 4 6 ns llc (is only available in synchronous output mode at a transport rate of 13.5 mhz.) t llc cycle time 37 ns f h pulse width 'high' 12 18 24 ns t h1 output signal hold time for pixclk 7 10 12 ns
vpx 3220 a, vpx 3216 b, vpx 3214 c preliminary data sheet micronas intermetall 67 symbol parameter min. typ. max. unit test conditions pixclk: asynchronous mode v il input voltage low 0.5 0.8 v v ih input voltage high for input pin pixclk 2.0 pvdd + 0.3 v v trhl trigger level at transition high to low 1.2 v v trlh trigger level at transition low to high 1.6 v f cycl cycle time 35 ns f h minimum pulse width 'high' ns f l minimum pulse width 'low' ns t d delay pixclk(input) to a [7:0] 11 ns b [7:0] 20 ns neg. edge of fe 20 ns pos. edge of hf tbd ns alpha 20 ns a special pvdd, pvss supply is used only to support the digital output pins. this means, inherently, that in case of tristate conditions, external sources should not drive these signals above the voltage pvdd which supplies the output pins. all timing specifications are based on the following assumptions: the load capacitance of the fast pins (output driver type a) is c a = 30 pf, the load capacitance of the remaining pins (output driver type b) is c b = 50 pf; no static currents are assumed; the driving capability of the pads is str = 4, which means that 5 of 8 output drivers are enabled. the typical case specification relates to: the ambient temperature is t a = 25 c, which relates to a junction temperature of t j = 70 c; the power supply of the pad circuits is pvdd = 3.3 v, and the power supply of the digital parts is vdd = 5.0 v. the best case specification relates to: a junction temperature of t j = 0 c; the power supply of the pad circuits is pvdd = 3.6 v, and the power supply of the digital parts is vdd = 5.25 v. the worst case specification relates to: a junction temperature of t j = 125 c; the power supply of the pad circuits is pvdd = 3.0 v, and the power supply of the digital parts is vdd = 4.75 v. rise times are specified as a transition between 0.6 v to 2.4 v. fall times are defined as a transition between 2.4 v to 0.6 v.
preliminary data sheet vpx 3220 a, vpx 3216 b, vpx 3214 c micronas intermetall 68 6.6.12.1. characteristics, synchronous mode, 13.5 mhz data rate, asingle clocko data and vact valid! llc pixclk a[7:0], vact b[7:0], alpha 37 ns 18.5 ns 0 ns 55.5 ns 74 ns 92.5 ns 111 ns 2.4 v 1.5 v 0.6 v 2.4 v 1.5 v 0.6 v 2.4 v 1.5 v 0.6 v 2.4 v 1.5 v 0.6 v t ra /t fa t rb /t fb t fa t h1 t h2 t fa t ra t llc detailed timing llc pixclk b[7:0], a[7:0] t ra t fa vact t ra 2.4 v 1.5 v 0.6 v alpha t h3
vpx 3220 a, vpx 3216 b, vpx 3214 c preliminary data sheet micronas intermetall 69 6.6.12.2. characteristics, synchronous mode, 20.25 mhz data rate, asingle clocko pixclk a[7:0], vact b[7:0], alpha 25 ns 0 ns 50 ns 75 ns 100 ns 2.4 v 1.5 v 0.6 v 2.4 v 1.5 v 0.6 v 2.4 v 1.5 v 0.6 v t ra /t fa t rb /t fb t h2 t fa t ra detailed timing pixclk b[7:0], a[7:0] t fa vact t ra 2.4 v 1.5 v 0.6 v alpha t clk20 t h3
preliminary data sheet vpx 3220 a, vpx 3216 b, vpx 3214 c micronas intermetall 70 6.6.12.3. characteristics, synchronous mode, 13.5 mhz data rate, adouble clocko pixclk a[7:0] vact alpha byte 1 byte 2 byte 1 byte 2 byte 1 byte 2 byte 1 byte 2 37 ns 18.5 ns 0 ns 55.5 ns 74 ns 92.5 ns 111 ns 2.4 v 1.5 v 0.6 v 2.4 v 1.5 v 0.6 v 2.4 v 1.5 v 0.6 v t ra /t fa t rb /t fb t h2 t fa t ra t clk13 detailed timing pixclk a[7:0] t fa vact t ra 2.4 v 1.5 v 0.6 v alpha t h2 b[7:0] t h3
vpx 3220 a, vpx 3216 b, vpx 3214 c preliminary data sheet micronas intermetall 71 6.6.12.4. characteristics, asynchronous mode if the digital video interface is in asynchronous mode, then the data transfer is controlled by an external clock signal. therefore, the interface signal pixclk is used as an input signal. the video data refers to the positive or negative slope of pixclk, depending on the setting of the i 2 c reg. f1 hex bit[2]. in asynchronous mode, the pixclk is always a single edge clock. if luma and chro- ma data should be transferred via a-port (double clock mode), then each data requires a complete clock cycle of pixclk. a complete pixel (luma and chroma) needs two complete clock cycles. pixclk (in) a[7:0], b[7:0], alpha pixclk (in) pos. edge triggered neg. edge triggered fe 25 ns 0 ns 50 ns 75 ns 100 ns 2.4 v 1.5 v 0.6 v 2.4 v 1.5 v 0.6 v 2.4 v 1.5 v 0.6 v t ra /t fa t rb /t fb t d detailed timing pixclk (in) b[7:0], a[7:0] t fa t ra 2.4 v 1.5 v 0.6 v alpha 2.4 v 1.5 v 0.6 v pixclk (in) pos. edge triggered neg. edge triggered f cycl f h f h f l f l t d* fe
preliminary data sheet vpx 3220 a, vpx 3216 b, vpx 3214 c micronas intermetall 72 start and end of an asynchronous transfer mode 1 2 3 4 5 6 7 8 9 101112131415161718192021 0 0 input pointer output pointer vact video data internal clock internal signals if half full level (i 2 c reg. f0 hex) is 15 pin signals note: the positive slope of fe and the negative slope of hf is determined by internal timing! there is no relation to any pin signal. pixclk hf fe n13 n12 n11 n10 n9 n8 n7 n6 n5 n4 n3 n2 n1 n n input pointer output pointer pixclk (input) internal signals if half full level (i 2 c reg. f0 hex) is 15 pin signals n14 n15 video data a[7:0], b[7:0] hf fe
vpx 3220 a, vpx 3216 b, vpx 3214 c preliminary data sheet micronas intermetall 73 6.6.13. characteristics, ttl output driver the drivers of the output pads are implemented as a par- allel connection of 8 tristate buffers of the same size. the buffers are enabled depending on the desired driver strength. this opportunity offers the advantage of adapt- ing the driver strength to on-chip and off-chip constraints, e.g. to minimize the noise resulting from steep signal transitions. the driving capability/strength is controlled by the state of the two i 2 c registers f8 hex and f9 hex . f8 pad driver strength ttl output pads type a bit [2:0] : driver strength of port a[7:0] bit [5:3] : driver strength of pixclk, hf and fe bit [7:6] : additional pixclk driver strength strength = bit [5:3] | {bit[7:6], 0} f9 pad driver strength ttl output pads type b bit [2:0] : driver strength of port b[7:0] bit [5:3] : driver strength of href, vref, pref and alpha/tdo strength 0 strength 1 strength 2 strength 3 strength 4 strength 5 strength 6 strength = 7 fig. 618: block diagram of the output stages
preliminary data sheet vpx 3220 a, vpx 3216 b, vpx 3214 c micronas intermetall 74 6.6.13.1. ttl output driver type a symbol parameter min. typ. max. unit test conditions t a 65 rt 0 c ambient temperature vdd, avdd 4.75 5.0 5.25 v supply pvdd 3.0 3.3 3.6 v pad supply t ra rise time 2 5 10 ns c l = 30 pf, strength = 5 t fa fall time 2 5 10 ns c l = 30 pf, strength = 5 i oh (0) output high current (strength = 0) 1.37 2.25 2.87 ma v oh = 0.6 v i ol (0) output low current (strength = 0) 1.75 3.5 4.5 ma v oh = 2.4 v i oh (7) output high current (strength = 7) 11 18 25 ma v oh = 0.6 v i ol (7) output low current (strength = 7) 14 28 36 ma v oh = 2.4 v c o high-impedance output capacitance 5 8 pf 6.6.13.2. ttl output driver type b symbol parameter min. typ. max. unit test conditions t a 65 rt 0 c ambient temperature vdd, avdd 4.75 5.0 5.25 v supply pvdd 3.0 3.3 3.6 v pad supply t rb rise time 6 12 25 ns c l = 50 pf, strength = 5 t fb fall time 6 12 25 ns c l =50 pf, strength = 5 i oh (0) output high current (strength = 0) 0.63 1.13 1.38 ma v oh = 2.4 v i ol (0) output low current (strength = 0) 0.81 1.81 2.38 ma v oh = 0.6 v i oh (7) output high current (strength = 7) 5 9 12 ma v oh = 2.4 v i ol (7) output low current (strength = 7) 6.5 14.5 19 ma v oh = 0.6 v c o high-impedance output capacitance 5 8 pf
vpx 3220 a, vpx 3216 b, vpx 3214 c preliminary data sheet micronas intermetall 75 6.6.14. characteristics, enable/disable of output signals in order to enable the output pins of the vpx to achieve the high impedance/tristate mode, various controls have been implemented. the following paragraphs give an overview of the different tristate modes of the output sig- nals. it is valid for all output pins, except the xtal2 (which is the oscillator output) and the vrt pin (which is an analog reference voltage). bs (boundary-scan) mode: the tristate control by the test access port tap for boundary-scan has the highest priority. even if the tap- controller is in the extest or clamp mode, the tristate behavior is only defined by the state of the different boundary scan registers for enable control. if the tap controller is in highz mode, then all output pins are in tristate mode independently of the state of the different boundary scan registers for enable control. reset state: if the tap-controller is not in the extest mode, then the reset-state defines the state of all digital outputs. the only exception is made for the data output of the bound- ary scan interface tdo. if the circuit is in reset condition (res = 0), then all output interfaces are in tristate mode. i 2 c control: the tristate condition of groups of signals can also be controlled by setting the i 2 c-register f2 hex . if the circuit is neither in extest mode nor reset state, then the i 2 c-register f2 hex defines whether the output is in tris- tate condition or not. the i 2 c-register #f1 uses differ- ent bits for different groups of outputs (see ai 2 c-register tableo). output enable input oe : the output enable signal oe only effects the video out- put ports. if the previous three conditions do not cause the output drivers to go into high impedance mode, then the oe signal defines the driving conditions of the video data ports. extest reset i 2 c oe# driver stages active output driver stages are defined by the state of the different boundary-scan enable registers. inactive active output drivers are in high impedance mode. inactive inactive = 0 output drivers are in high impedance mode. pixclk is working. inactive inactive = 1 output drivers href, vref, pref, fe , hf are working. inactive inactive = 1 = 1 output drivers of alpha, a[7:0], b[7:0], and c[7:0] are in high impedance mode. inactive inactive = 1 = 0 outputs alpha, a[7:0], b[7:0], and c[7:0] are working remark: extest mode is an instruction conforming to the standard for boundary-scan test ieee 1149.1 1990
preliminary data sheet vpx 3220 a, vpx 3216 b, vpx 3214 c micronas intermetall 76 output enable by pin oe oe signals a[7:0], b[7:0], alpha t off t on symbol parameter min. typ. max. unit test conditions v il input voltage low 0.5 0.8 v v ih input voltage high for input pins oe , res 2.0 6 v v trhl trigger level at transition high to low 1.2 v v trlh trigger level at transition low to high 1.6 v t on output enable oe of a[7:0], b[7:0], alpha 6 ns t off output disable oe of a[7:0], b[7:0], al- pha 8 ns
vpx 3220 a, vpx 3216 b, vpx 3214 c preliminary data sheet micronas intermetall 77 video pixel decoder family addendum 1. introduction for addendum vpx 3214c has two additional features compared to the vpx 3220a and vpx 3216b: another output timing mode called newvact and low power mode. 2. new output timing newvact the vpx family operates with a system and sampling clock of 20.25 mhz. when the oscillator is not locked to the line frequency of the processed video signal, the number of samples per video scan line can vary from line to line. the href signal marks the active video line and has a fixed width of 1056 clocks. the inactive part of the href can therefore vary in length. the same principle applies to the vact signal, the difference being that the active length of vact equals the number of output pixels times transport rate of either 20.25 or 13.5 mhz. this be- havior of href and vact signals is well suited for the systems using state machines to handle these signals and data delivered from vpx. on the other hand this be- havior causes problems in case the system uses plain counters to decide when to strobe the data. these sys- tems require that the inactive period of href also has a fixed length: they use the inactive going edge of href to reset their counters, count afterwards a certain amount of clocks and then strobe the preprogrammed number of data almost regardless of the state of vact signal. that's why this new timing mode was introduced. in this mode signal at vact pin has an unpredictable be- havior and newvact signal is available at the href pin carrying all the information. it goes inactive, stays inac- tive for the programmable number of transport rate clocks. this inactive phase is at least 8 clocks long and can be extended in clock units to the maximum length of 23 by writing the field [3:0] of the ofifo register (i 2 c ad- dress 0xf0). after that newvact goes active exactly before the first valid video data, so it still can be used as qualifier for the start of data. it stays active for the rest of the line regardless of the number of valid video data, so it can not be used as the end-qualifier. the system us- ing the data has to count properly and strobe only the valid data. after reset, the vpx operates in its usual output timing mode. there are two registers controlling the new mode. the fp register is used to switch it on and off and i 2 c register is used to control the length of the href inactive period. symbol parameter min. typ. max. unit test conditions t hnvl hold time of inactive going newvact after pixclk 20 ns t hnvh hold time of active going newvact after pixclk 15 ns t hv hold time of vref change after pixclk 10 ns newvacttiming (13.5/20.25mhz) pixclk href vref data oddfield changes evenfield changes 1. data 2. data ......
vpx 3220 a, vpx 3216 b, vpx 3214 c preliminary data sheet micronas intermetall 78 2.4 v 1.5 v 0.6 v detailed timing inactive going newvact and both vref edges in even field pixclk newvact 2.4 v 1.5 v 0.6 v (on href pin) vref 2.4 v 1.5 v 0.6 v t hv t hnvl 2.4 v 1.5 v 0.6 v detailed timing active going newvact and both vref edges in odd field pixclk newvact 2.4 v 1.5 v 0.6 v (on href pin) vref 2.4 v 1.5 v 0.6 v t hv t hnvh i 2 c reg. address number of bits mode function name f0 8 w output fifo ofifo fifo control: (only available in asynchronous mode) bit [4:0] : fifo flag half full level (interface signal hf ) hfull newvact control: (only available in synchronous mode) bit [3:0] : additional length of newvact inactive period. total length in clocks equals 8 + bit[3:0] bit [4] : reserved (must be set to zero) bit [7:5] : bus shuffler 000 out[23:0] = in[23:0] 001, 010 out[23:0] = in[7:0, 23:8] 011 out[23:0] = in[15:0, 23:16] 100 out[23:0] = in[15:8, 23:16, 7:0] 101, 110 out[23:0] = in[7:0, 15:8, 23:16] 111 out[23:0] = in[23:16, 7:0, 15:8] meaning: in[23:0] : data from color space stage out[23:0] : data to output fifo shuf the control register modes are w: write/read register r: read-only register d: register is double latched v: register is latched with vsync a: register is available only in vpx 3220 a; vpx 3216 b returns valid ack, although no internal action is performed the mnemonics used in the intermetall vpx demo software are given in the last column.
vpx 3220 a, vpx 3216 b, vpx 3214 c preliminary data sheet micronas intermetall 79 3. low power mode in order to accommodate power consumption critical ap- plications, low power mode is introduced. it can be turned on and off through the i 2 c register 0xaa. there are three levels of low power. when any of them is turned on, vpx waits for at least one complete video scan line in order to complete all internal tasks and then goes into three-state mode. the exact moment is not precisely defined, so care should be taken to deactivate the system using vpx data before the end of the video scan line in which vpx is switched into low power mode. during the low power mode all the i 2 c and fp registers are preserved, so that vpx restores its normal operation as soon as low power mode is turned off without need for any reinitialization. on the other hand all the i 2 c and fp registers can be read / written as usual. the only excep- tion is the third level (value of 3 in i 2 c register 0xaa) of low power. in that mode, i 2 c speeds above 100 kbit/sec are not allowed. in modes 1 and 2, i 2 c can be used up to the full speed of 400 kbit/sec. i 2 c reg. address number of bits mode function name aa 8 w low power bit [1:0] : low power 00 active mode 01 outputs threestated; clock divided by 2; i 2 c full speed 10 outputs threestated; clock divided by 4; i 2 c full speed 11 outputs threestated; clock divided by 8; i 2 c only up to 100 kbit/sec lowpow the control register modes are w: write/read register r: read-only register d: register is double latched v: register is latched with vsync a: register is available only in vpx 3220 a; vpx 3216 b returns valid ack, although no internal action is performed the mnemonics used in the intermetall vpx demo software are given in the last column.
preliminary data sheet vpx 3220 a, vpx 3216 b, vpx 3214 c micronas intermetall 80 4. data sheet history 1. data sheet avpx 3220 a, vpx 3216 b video pixel decodero, aug. 25, 1995, 6251-368-1pd: first prelimi- nary release of the data sheet. 2. data sheet avpx 3220 a, vpx 3216 b, vpx 3214 c video pixel decoderso, july 1, 1996, 6251-368-2pd: second preliminary release of the data sheet. major changes: vpx 3214 c has been included fig. 61: package dimensions changed micronas intermetall gmbh hans-bunte-strasse 19 d-79108 freiburg (germany) p.o. box 840 d-79008 freiburg (germany) tel. +49-761-517-0 fax +49-761-517-2174 e-mail: docservice@intermetall.de internet: http://www.intermetall.de printed in germany order no. 6251-368-2pd all information and data contained in this data sheet are with- out any commitment, are not to be considered as an offer for conclusion of a contract nor shall they be construed as to create any liability. any new issue of this data sheet invalidates previous issues. product availability and delivery dates are ex- clusively subject to our respective order confirmation form; the same applies to orders based on development samples deliv- ered. by this publication, micronas intermetall gmbh does not assume responsibility for patent infringements or other rights of third parties which may result from its use. reprinting is generally permitted, indicating the source. how- ever, our prior consent must be obtained in all cases.

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